From: Shannon Zhao <[email protected]>

Since the reset value of PMSELR_EL0 is UNKNOWN, use reset_unknown for
its reset handler. Add access handler which emulates writing and reading
PMSELR_EL0 register.

Signed-off-by: Shannon Zhao <[email protected]>
---
 arch/arm64/kvm/sys_regs.c | 26 +++++++++++++++++++++++++-
 1 file changed, 25 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 152ee17..69c8c48 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -275,6 +275,30 @@ static bool access_pmcr(struct kvm_vcpu *vcpu,
        return true;
 }
 
+/* PMSELR_EL0 accessor. */
+static bool access_pmselr(struct kvm_vcpu *vcpu,
+                         const struct sys_reg_params *p,
+                         const struct sys_reg_desc *r)
+{
+       unsigned long val;
+
+       if (p->is_write) {
+               val = *vcpu_reg(vcpu, p->Rt);
+               if (!p->is_aarch32)
+                       vcpu_sys_reg(vcpu, r->reg) = val;
+               else
+                       vcpu_cp15(vcpu, r->reg) = val & 0xffffffffUL;
+       } else {
+               if (!p->is_aarch32)
+                       val = vcpu_sys_reg(vcpu, r->reg);
+               else
+                       val = vcpu_cp15(vcpu, r->reg);
+               *vcpu_reg(vcpu, p->Rt) = val;
+       }
+
+       return true;
+}
+
 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
 #define DBG_BCR_BVR_WCR_WVR_EL1(n)                                     \
        /* DBGBVRn_EL1 */                                               \
@@ -481,7 +505,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
          trap_raz_wi },
        /* PMSELR_EL0 */
        { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101),
-         trap_raz_wi },
+         access_pmselr, reset_unknown, PMSELR_EL0 },
        /* PMCEID0_EL0 */
        { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),
          trap_raz_wi },
-- 
2.1.0

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