On 10/29/2015 12:31 AM, Xiao Guangrong wrote:
> These instructions are used by NVDIMM drivers and the specification
> locates at:
> https://software.intel.com/sites/default/files/managed/0d/53/319433-022.pdf
> There instructions are available on Skylake Server
> Signed-off-by: Xiao Guangrong <guangrong.x...@linux.intel.com>
> ---
>  target-i386/cpu.c | 8 +++++---
>  target-i386/cpu.h | 3 +++
>  2 files changed, 8 insertions(+), 3 deletions(-)

Reviewed-by: Richard Henderson <r...@twiddle.net>

Although it would be nice to update the comments in translate.c to include the
new insns, since they overlap mfence and sfence.  At present we only check for
SSE enabled when accepting these; I suppose it's easiest to consider it invalid
to specify +clwb,-sse?

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