From: Shannon Zhao <shannon.z...@linaro.org>

Since the reset value of PMINTENSET and PMINTENCLR is UNKNOWN, use
reset_unknown for its reset handler. Add a new case to emulate writing
PMINTENSET or PMINTENCLR register.

Signed-off-by: Shannon Zhao <shannon.z...@linaro.org>
---
 arch/arm64/kvm/sys_regs.c | 34 ++++++++++++++++++++++++++++++----
 1 file changed, 30 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index e852e5d..a4f9177 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -547,6 +547,18 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu,
                        vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;
                        break;
                }
+               case PMINTENSET_EL1: {
+                       val = *vcpu_reg(vcpu, p->Rt);
+                       vcpu_sys_reg(vcpu, r->reg) |= val;
+                       vcpu_sys_reg(vcpu, PMINTENCLR_EL1) |= val;
+                       break;
+               }
+               case PMINTENCLR_EL1: {
+                       val = *vcpu_reg(vcpu, p->Rt);
+                       vcpu_sys_reg(vcpu, r->reg) &= ~val;
+                       vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val;
+                       break;
+               }
                case PMCR_EL0: {
                        /* Only update writeable bits of PMCR */
                        val = vcpu_sys_reg(vcpu, r->reg);
@@ -742,10 +754,10 @@ static const struct sys_reg_desc sys_reg_descs[] = {
 
        /* PMINTENSET_EL1 */
        { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b001),
-         trap_raz_wi },
+         access_pmu_regs, reset_unknown, PMINTENSET_EL1 },
        /* PMINTENCLR_EL1 */
        { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b010),
-         trap_raz_wi },
+         access_pmu_regs, reset_unknown, PMINTENCLR_EL1 },
 
        /* MAIR_EL1 */
        { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0010), Op2(0b000),
@@ -1079,6 +1091,18 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu,
                        vcpu_cp15(vcpu, c9_PMCNTENSET) &= ~val;
                        break;
                }
+               case c9_PMINTENSET: {
+                       val = *vcpu_reg(vcpu, p->Rt);
+                       vcpu_cp15(vcpu, r->reg) |= val;
+                       vcpu_cp15(vcpu, c9_PMINTENCLR) |= val;
+                       break;
+               }
+               case c9_PMINTENCLR: {
+                       val = *vcpu_reg(vcpu, p->Rt);
+                       vcpu_cp15(vcpu, r->reg) &= ~val;
+                       vcpu_cp15(vcpu, c9_PMINTENSET) &= ~val;
+                       break;
+               }
                case c9_PMCR: {
                        /* Only update writeable bits of PMCR */
                        val = vcpu_cp15(vcpu, r->reg);
@@ -1178,8 +1202,10 @@ static const struct sys_reg_desc cp15_regs[] = {
        { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_cp15_regs,
          NULL, c9_PMXEVCNTR },
        { Op1( 0), CRn( 9), CRm(14), Op2( 0), trap_raz_wi },
-       { Op1( 0), CRn( 9), CRm(14), Op2( 1), trap_raz_wi },
-       { Op1( 0), CRn( 9), CRm(14), Op2( 2), trap_raz_wi },
+       { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pmu_cp15_regs,
+         NULL, c9_PMINTENSET },
+       { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pmu_cp15_regs,
+         NULL, c9_PMINTENCLR },
 
        { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },
        { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
-- 
2.0.4


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