On Tue, May 12, 2009 at 09:20:36AM -0400, Beth Kon wrote:
> Gleb Natapov wrote:
>> On Tue, May 12, 2009 at 01:22:06PM +0300, Avi Kivity wrote:
>>
>>> Gleb Natapov wrote:
>>>
>>>>> for (i = 0; i < 24; ++i) {
>>>>> - r = kvm_add_irq_route(kvm_context, i, KVM_IRQCHIP_IOAPIC, i);
>>>>> + if (i == 0) {
>>>>> + r = kvm_add_irq_route(kvm_context, i,
>>>>> KVM_IRQCHIP_IOAPIC, 2);
>>>>> + } else if (i != 2) {
>>>>> + r = kvm_add_irq_route(kvm_context, i,
>>>>> KVM_IRQCHIP_IOAPIC, i);
>>>>> + }
>>>>>
>>>> There is no entry for IRQ2, is this OK? What happens if IRQ2 triggers?
>>>>
>>> irq 2 is the PIC cascade interrupt. If it is somehow triggered, the
>>> kernel will ignore it.
>>>
>>>
>> But here we configure IOAPIC routing. What if IOAPIC is used for
>> interrupt delivery and something triggers irq2. There is no entry
>> describing it in IOAPIC routing table, so what gsi it will be mapped to?
>>
>> --
>>
> The ACPI spec states that systems that support both APIC and dual-8259
> interrupt models must map system interrupt vectors 0-15 to 8259 IRQs
> 0-15, except where interrupt source overrides are provided. We provide
> an irq0->inti2 override, and no irq2 override, so irq2 must be unused.
OK. I hope we do what ACPI spec states and irq2 never reaches IOAPIC.
--
Gleb.
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