Nitin A Kamble wrote: > As per the IA32 processor manual, the accessed bit is set to 1 in the > processor state after reset. qemu pc cpu_reset code was missing this > accessed bit setting. > > Signed-off-by: Nitin A Kamble <[email protected]> > --- > target-i386/helper.c | 18 ++++++++++++------ > 1 files changed, 12 insertions(+), 6 deletions(-) > > diff --git a/target-i386/helper.c b/target-i386/helper.c > index 7fc5366..573fb5b 100644 > --- a/target-i386/helper.c > +++ b/target-i386/helper.c > @@ -493,17 +493,23 @@ void cpu_reset(CPUX86State *env) > env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); > > cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, > - DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | > DESC_R_MASK); > + DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | > + DESC_R_MASK | DESC_A_MASK); > cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, > - DESC_P_MASK | DESC_S_MASK | DESC_W_MASK); > + DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | > + DESC_A_MASK); > cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, > - DESC_P_MASK | DESC_S_MASK | DESC_W_MASK); > + DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | > + DESC_A_MASK); > cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, > - DESC_P_MASK | DESC_S_MASK | DESC_W_MASK); > + DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | > + DESC_A_MASK); > cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, > - DESC_P_MASK | DESC_S_MASK | DESC_W_MASK); > + DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | > + DESC_A_MASK); > cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, > - DESC_P_MASK | DESC_S_MASK | DESC_W_MASK); > + DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | > + DESC_A_MASK); > > env->eip = 0xfff0; > env->regs[R_EDX] = env->cpuid_version;
Acked-by: Jan Kiszka <[email protected]> Thanks, Jan
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