Hi Marcelo,

Thanks for your review.

Marcelo Tosatti wrote:
> On Wed, Mar 17, 2010 at 11:43:06AM +0800, Xiao Guangrong wrote:
>> - The RSV bit is possibility set in error code when #PF occurred
>>   only if CR4.PSE=1 or CR4.PAE=1
>>   
>> - context->rsvd_bits_mask[1][0] is always 0
>>
>> Changlog:
>> Move this operation to reset_rsvds_bits_mask() address Avi Kivity's 
>> suggestion
>>
>> Signed-off-by: Xiao Guangrong <[email protected]>
>> ---
>>  arch/x86/kvm/mmu.c |   12 +++++++++---
>>  1 files changed, 9 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c
>> index b137515..c49f8ec 100644
>> --- a/arch/x86/kvm/mmu.c
>> +++ b/arch/x86/kvm/mmu.c
>> @@ -2288,18 +2288,26 @@ static void reset_rsvds_bits_mask(struct kvm_vcpu 
>> *vcpu, int level)
>>  
>>      if (!is_nx(vcpu))
>>              exb_bit_rsvd = rsvd_bits(63, 63);
>> +
>> +    context->rsvd_bits_mask[1][0] = 0;
> 
> So if the guest enables PAT at PTE level you completly disable reserved
> bit checking? You should only disable checking for [1][1] if !PSE.

Sorry, i make a mistake here because i see the current code is redundant:
        context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0];
in every case.

This code is imported by commit fd2e987d, i think this is Avi Kivity's typo :-)
i think the correct way is:
        ontext->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];

I'll send a new version patch to fix it if you not object. 

Xiao


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