On 07/13/10 15:15, Zachary Amsden wrote:
>> What prevents a vcpu from seeing its TSC go backwards, in case the first >> write in the 5 second window is smaller than the victim vcpu's last >> visible TSC value ? >> > > Nothing, unfortunately. However, the TSC would already have to be out > of sync in order for the problem to occur. It can never happen in > normal circumstances on a stable hardware TSC except in one case; > migration. During the CPU state transfer phase of migration, however, What about across processor sockets? Aren't CPUs brought up at different points such that their TSCs start at different times? David -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
