Ulrich Drepper wrote:
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On 08/02/2010 05:51 AM, Andre Przywara wrote:
Do you have a use case for the cache size or is this just out of curiosity?
glibc uses the cache size information returned by cpuid to perform
optimizations. For instance, copy operations which would pollute too
much of the cache because they are large will use non-temporal
instructions. There are real performance benefits.
Thanks for pointing this out. Do you have an idea which benchmark could
show the impact of an incorrect cache size? Microbenchmarks would be OK,
as long as it can convince maintainers ;-)
> Even the synthetic
CPU provided by qemu should have a more realistic value.
What would you recommend as a more realistic value?
For AMD it is currently 64K/64K C/D for L1 and 512KB for L2, for Intel
32K/32K C/D for L1 and 4MB for L2.
I think the 32KB shown in the original post are some kind of a bug,
Ricardo, can you reproduce this? Can you post the command line and the
used qemu version ($ qemu --version)
Regards,
Andre.
--
Andre Przywara
AMD-Operating System Research Center (OSRC), Dresden, Germany
Tel: +49 351 488-3567-12
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