On 08/30/2010 11:20 AM, Avi Kivity wrote:
Otherwise, a wily interrupt can slip through while the guest isn't prepared
for it (and while the irq base is zero).
Signed-off-by: Avi Kivity<[email protected]>
---
arch/x86/kvm/i8259.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/x86/kvm/i8259.c b/arch/x86/kvm/i8259.c
index 8d10c06..5de9ee0 100644
--- a/arch/x86/kvm/i8259.c
+++ b/arch/x86/kvm/i8259.c
@@ -275,7 +275,7 @@ void kvm_pic_reset(struct kvm_kpic_state *s)
s->last_irr = 0;
s->irr = 0;
- s->imr = 0;
+ s->imr = 0xff;
s->isr = 0;
s->isr_ack = 0xff;
s->priority_add = 0;
Sounds sane, but the datasheet says explicitly that upon reset "The
Interrupt Mask Register is cleared"... (FWIW, I checked because it
looked like QEMU and Xen also had the same behavior of setting IMR to zero).
Paolo
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