Marcelo Tosatti wrote:
>>> --- a/arch/x86/include/asm/msr-index.h
>>> +++ b/arch/x86/include/asm/msr-index.h
>>> @@ -229,6 +229,8 @@
>>>  #define MSR_IA32_APICBASE_ENABLE   (1<<11)
>>>  #define MSR_IA32_APICBASE_BASE             (0xfffff<<12)
>>> 
>>> +#define MSR_IA32_TSCDEADLINE               0x000006e0
>>> +
>>>  #define MSR_IA32_UCODE_WRITE               0x00000079
>>>  #define MSR_IA32_UCODE_REV         0x0000008b
>> 
>> Need to add to msrs_to_save so live migration works.
> 
> MSR must be explicitly listed in qemu, also.
> 

OK

>>> +           if (!apic->lapic_timer.tscdeadline)
>>> +                   return;
>>> +
>>> +           tsc_target = kvm_x86_ops->
>>> +                   guest_to_host_tsc(apic->lapic_timer.tscdeadline);
>>> +           rdtscll(tsc_now); +             tsc_delta = tsc_target - 
>>> tsc_now;
>> 
>> This only works if we have a constant tsc, that's not true for large
>> multiboard machines.  Need to do this with irqs disabled as well
>> (reading both 'now' and 'tsc_now' in the same critical section).
> 
> Should look like this:
> 
> local_irq_disable();
> u64 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
> if (guest_tsc <= tscdeadline)
>         hrtimer_start(now);
> else {
>       ns = convert_to_ns(guest_tsc - tscdeadline);
>       hrtimer_start(now + ns);
> }
> local_irq_enable();
> 
> Note the vcpus tsc can have different frequency than the hosts, so
> vcpu_tsc_khz() should be used to convert to nanoseconds, not tsc_khz.
> 

Fine.


Thanks,
Jinsong--
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