On Tue, Sep 20, 2011 at 04:56:02PM +0300, Avi Kivity wrote:
> On 09/20/2011 04:25 PM, Marcelo Tosatti wrote:
> >>
> >> @@ -2827,6 +2828,7 @@ static int kvm_vcpu_ioctl_x86_set_mce(struct
> >> kvm_vcpu *vcpu,
> >> static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
> >> struct kvm_vcpu_events *events)
> >> {
> >> + process_nmi(vcpu);
> >> events->exception.injected =
> >> vcpu->arch.exception.pending&&
> >> !kvm_exception_is_soft(vcpu->arch.exception.nr);
> >> @@ -2844,7 +2846,7 @@ static void
> >> kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
> >> KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
> >>
> >> events->nmi.injected = vcpu->arch.nmi_injected;
> >> - events->nmi.pending = vcpu->arch.nmi_pending;
> >> + events->nmi.pending = vcpu->arch.nmi_pending != 0;
> >> events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
> >> events->nmi.pad = 0;
> >
> >nmi_queued should also be saved and restored. Not sure if its necessary
> >though.
> >
> >Should at least reset nmi_queued somewhere (set_vcpu_events?).
>
> Did you miss the call to process_nmi()?
It transfers nmi_queued to nmi_pending with capping. What i mean is that
upon system reset, nmi_queued (which refers to pre-reset system state)
should be zeroed.
> We do have a small issue. If we exit during NMI-blocked-by-STI and
> nmi_pending == 2, then we lose the second interrupt. Should rarely
> happen, since external interrupts never exit in that condition, but
> it's a wart.
And the above system reset case, you should be able to handle it by
saving/restoring nmi_queued (so that QEMU can zero it in vcpu_reset).
> >
> >> @@ -2864,6 +2866,7 @@ static int
> >> kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
> >> | KVM_VCPUEVENT_VALID_SHADOW))
> >> return -EINVAL;
> >>
> >> + process_nmi(vcpu);
> >
> >This should be after nmi fields are set, not before?
> >
>
> It's actually to clear queued NMIs in case we set nmi_pending (which
> should never happen unless the machine is completely quiet, since
> it's asynchronous to the vcpu; same as the IRR).
OK.
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