On Sun, May 13, 2012 at 06:56:23PM +0300, Gleb Natapov wrote:
> > + However, hypervisor can set and clear this memory bit at any time:
> > + therefore to make sure hypervisor does not interrupt the
> > + guest and clear the least significant bit in the memory area
> > + in the window between guest testing it to detect
> > + whether it can skip EOI apic write and between guest
> > + clearing it to signal EOI to the hypervisor,
> > + guest must both read the least sgnificant bit in the memory area and
> > + clear it using a single CPU instruction, such as test and clear, or
> > + compare and exchange.
> > +
> Looks good, but everything below this is here by mistake.
Ugh. Right. Good catch,
> Are You still
> going to resend host side patch to address my other comment?
Yes, like this.
I'll give more people a chance to review first though.
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index 77e0244..c7e6ffb 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -1490,6 +1490,7 @@ int kvm_pv_enable_apic_eoi(struct kvm_vcpu *vcpu, u64
data)
if (eoi_enabled(vcpu))
eoi_clr_pending(vcpu);
vcpu->arch.eoi.msr_val = data;
- kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.eoi.data, addr);
- return 0;
+ if (!eoi_enabled(vcpu))
+ return 0;
+ return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.eoi.data, addr);
}
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