> -----Original Message-----
> From: Marcelo Tosatti [mailto:[email protected]]
> Sent: Tuesday, May 15, 2012 10:20 AM
> To: Mao, Junjie
> Cc: Eric Northup; [email protected]
> Subject: Re: [PATCH] KVM: x86: Implement PCID/INVPCID for guests with EPT
> 
> On Mon, May 14, 2012 at 07:15:18AM +0000, Mao, Junjie wrote:
> > > On Wed, May 9, 2012 at 5:32 PM, Mao, Junjie <[email protected]>
> wrote:
> > > > This patch handles PCID/INVPCID for guests.
> > > >
> > > > Process-context identifiers (PCIDs) are a facility by which a logical
> processor may cache information for multiple linear-address spaces so that the
> processor may retain cached information when software switches to a
> different linear-address space. Refer to section 4.10.1 in IA32 Intel Software
> Developer's Manual Volume 3A for details.
> > > >
> > > > For guests with EPT, the PCID feature is enabled and INVPCID behaves as
> running natively.
> > > > For guests without EPT, the PCID feature is disabled and INVPCID 
> > > > triggers
> #UD.
> > > >
> > > Do I understand correctly that this means it is impossible to migrate a
> guest which is using PCID from a host with EPT to a host without EPT (by
> passing enable_ept=0 to the module, for example) ?
> >
> > I think you are right. Guests using PCID/INVPCID cannot migrate to a host
> without it, and EPT is a precondition of this feature.
> 
> Are there processors that support PCI/INVPCID for the host but lack support
> for SECONDARY_EXEC_ENABLE_INVPCID?

There're some with PCID but without INVPCID. For those processors support 
INVPCID, SECONDARY_EXEC_ENABLE_INVPCID support should be present. As PCID has 
little benefits without INVPCID, these two features are exposed/hidden as a 
whole.

> 
> > > Does the emulated CR3 load need to learn about the new function of the
> low bits?
> >
> > I have not found any restrictions on writing CR3 brings about by PCID.
> 
> It would be good for completeness.
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