[PATCH 5/5]KVM:x86, apicv: add virtual x2apic support

[Li, Jiongxi]

basically to benefit from apicv, we need clear MSR bitmap for
corresponding x2apic MSRs:
    0x800 - 0x8ff: no read intercept for apicv register virtualization
    TPR,EOI,SELF-IPI: no write intercept for virtual interrupt delivery

Signed-off-by: Kevin Tian <kevin.t...@intel.com>
Signed-off-by: Jiongxi Li <jiongxi...@intel.com>
---
 arch/x86/kvm/vmx.c |   46 +++++++++++++++++++++++++++++++++++++++-------
 1 files changed, 39 insertions(+), 7 deletions(-)

diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 73ff537..2db1ddc 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -3724,7 +3724,9 @@ static void free_vpid(struct vcpu_vmx *vmx)
        spin_unlock(&vmx_vpid_lock);
 }
 
-static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
+#define MSR_TYPE_R     1
+#define MSR_TYPE_W     2
+static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 
msr, int type)
 {
        int f = sizeof(unsigned long);
 
@@ -3737,20 +3739,38 @@ static void __vmx_disable_intercept_for_msr(unsigned 
long *msr_bitmap, u32 msr)
         * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
         */
        if (msr <= 0x1fff) {
-               __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
-               __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
+               if (type & MSR_TYPE_R)
+                       __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
+               if (type & MSR_TYPE_W)
+                       __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low 
*/
        } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
                msr &= 0x1fff;
-               __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
-               __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
+               if (type & MSR_TYPE_R)
+                       __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high 
*/
+               if (type & MSR_TYPE_W)
+                       __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high 
*/
        }
 }
 
 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
 {
        if (!longmode_only)
-               __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
-       __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
+               __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr, 
MSR_TYPE_R | MSR_TYPE_W);
+       __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr, 
MSR_TYPE_R | MSR_TYPE_W);
+}
+
+static void vmx_disable_intercept_for_msr_read(u32 msr, bool longmode_only)
+{
+       if (!longmode_only)
+               __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr, 
MSR_TYPE_R);
+       __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr, 
MSR_TYPE_R);
+}
+
+static void vmx_disable_intercept_for_msr_write(u32 msr, bool longmode_only)
+{
+       if (!longmode_only)
+               __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr, 
MSR_TYPE_W);
+       __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr, 
MSR_TYPE_W);
 }
 
 /*
@@ -7524,6 +7544,18 @@ static int __init vmx_init(void)
        vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
        vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
 
+       if (enable_apicv_reg) {
+               int msr;
+               for (msr = 0x800; msr <= 0x8ff; msr++)
+                       vmx_disable_intercept_for_msr_read(msr, false);
+       }
+
+       if (enable_apicv_vid) {
+               vmx_disable_intercept_for_msr_write(0x808, false); // TPR
+               vmx_disable_intercept_for_msr_write(0x80b, false); // EOI
+               vmx_disable_intercept_for_msr_write(0x83f, false); // SELF-IPI
+       }
+
        if (enable_ept) {
                kvm_mmu_set_mask_ptes(0ull,
                        (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
-- 
1.7.1

--
To unsubscribe from this list: send the line "unsubscribe kvm" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html