On 09/16/2012 08:07 PM, Avi Kivity wrote: > While unspecified, the behaviour of Intel processors is to first > perform the page table walk, then, if the walk was successful, to > atomically update the accessed and dirty bits of walked paging elements. > > While we are not required to follow this exactly, doing so will allow us > to perform the access permissions check after the walk is complete, rather > than after each walk step. > > (the tricky case is SMEP: a zero in any pte's U bit makes the referenced > page a supervisor page, so we can't fault on a one bit during the walk > itself).
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