> -----Original Message-----
> From: Avi Kivity [mailto:[email protected]]
> Sent: Friday, September 07, 2012 12:02 AM
> To: Li, Jiongxi
> Cc: [email protected]
> Subject: Re: [PATCH 1/5]KVM: x86, apicv: add APICv register virtualization
> support
>
> On 09/05/2012 08:41 AM, Li, Jiongxi wrote:
> > - APIC read doesn't cause VM-Exit
> > - APIC write becomes trap-like
> >
> >
> > +/* emulate APIC access in a trap manner */ int
> > +kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset) {
> > + u32 val;
> > +
> > + /* hw has done the conditional check and inst decode */
> > + offset &= 0xff0;
> > + if ((offset != APIC_EOI) &&
> > + apic_reg_read(vcpu->arch.apic, offset, 4, &val))
> > + return 1;
>
> TMICT is a write-only register IIRC.
>
> > +
> > + /* TODO: optimize to just emulate side effect w/o one more write */
> > + return apic_reg_write(vcpu->arch.apic, offset, val);
>
> val may be uninitialized here.
>
> > +}
> > +EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
> > +
> > void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu) {
> >
> > +static bool __read_mostly enable_apicv_reg = 0;
>
> Enable by default.
>
> > +module_param(enable_apicv_reg, bool, S_IRUGO);
>
> Let's have one module parameter for all related features, called apicv.
> So modeprobe kvm-intel apicv=0 disables it.
>
> >
> > +static int handle_apic_write(struct kvm_vcpu *vcpu) {
> > + unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
> > + u32 offset = exit_qualification & 0xfff;
> > +
> > + /* APIC-write VM exit is trap-like and thus no need to adjust IP */
> > + return kvm_apic_write_nodecode(vcpu, offset) == 0; }
>
> Return 1 here means exit to userspace. This will go crazy.
>
> You need to return 0 always. If this is an msr write to a read-only
> register, you
> need to inject a #GP (IIRC).
Return 0 means exit to userspace, so it should return 1, right?
__vcpu_run
{
while (r>0)
{
r = vcpu_enter_guest(vcpu)
if (r<=0)
break;
}
}
>
>
>
> --
> error compiling committee.c: too many arguments to function
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