This adds the ability for userspace to save and restore the state
of the XICS interrupt presentation controllers (ICPs) via the
KVM_GET/SET_ONE_REG interface.  Since there is one ICP per vcpu, we
simply define a new 64-bit register in the ONE_REG space for the ICP
state.  The state includes the CPU priority setting, the pending IPI
priority, and the priority and source number of any pending external
interrupt.

Signed-off-by: Paul Mackerras <[email protected]>
---
 arch/powerpc/include/asm/kvm_ppc.h  |    2 +
 arch/powerpc/include/uapi/asm/kvm.h |   11 +++++
 arch/powerpc/kvm/book3s.c           |   18 +++++++
 arch/powerpc/kvm/book3s_xics.c      |   90 +++++++++++++++++++++++++++++++++++
 4 files changed, 121 insertions(+)

diff --git a/arch/powerpc/include/asm/kvm_ppc.h 
b/arch/powerpc/include/asm/kvm_ppc.h
index a9ab748..d00d7c3 100644
--- a/arch/powerpc/include/asm/kvm_ppc.h
+++ b/arch/powerpc/include/asm/kvm_ppc.h
@@ -176,6 +176,8 @@ extern int kvmppc_xics_set_xive(struct kvm *kvm, u32 irq, 
u32 server, u32 priori
 extern int kvmppc_xics_get_xive(struct kvm *kvm, u32 irq, u32 *server, u32 
*priority);
 extern int kvmppc_xics_int_on(struct kvm *kvm, u32 irq);
 extern int kvmppc_xics_int_off(struct kvm *kvm, u32 irq);
+extern u64 kvmppc_xics_get_icp(struct kvm_vcpu *vcpu);
+extern int kvmppc_xics_set_icp(struct kvm_vcpu *vcpu, u64 icpval);
 
 /*
  * Cuts out inst bits with ordering according to spec.
diff --git a/arch/powerpc/include/uapi/asm/kvm.h 
b/arch/powerpc/include/uapi/asm/kvm.h
index 55c1907..9fc1d11 100644
--- a/arch/powerpc/include/uapi/asm/kvm.h
+++ b/arch/powerpc/include/uapi/asm/kvm.h
@@ -425,4 +425,15 @@ struct kvm_book3e_206_tlb_params {
 #define KVM_REG_PPC_VPA_SLB    (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x83)
 #define KVM_REG_PPC_VPA_DTL    (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x84)
 
+/* Per-vcpu interrupt controller state */
+#define KVM_REG_PPC_ICP_STATE  (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x85)
+#define  KVM_REG_PPC_ICP_CPPR_SHIFT    56      /* current proc priority */
+#define  KVM_REG_PPC_ICP_CPPR_MASK     0xff
+#define  KVM_REG_PPC_ICP_XISR_SHIFT    32      /* interrupt status field */
+#define  KVM_REG_PPC_ICP_XISR_MASK     0xffffff
+#define  KVM_REG_PPC_ICP_MFRR_SHIFT    24      /* pending IPI priority */
+#define  KVM_REG_PPC_ICP_MFRR_MASK     0xff
+#define  KVM_REG_PPC_ICP_PPRI_SHIFT    16      /* pending irq priority */
+#define  KVM_REG_PPC_ICP_PPRI_MASK     0xff
+
 #endif /* __LINUX_KVM_POWERPC_H */
diff --git a/arch/powerpc/kvm/book3s.c b/arch/powerpc/kvm/book3s.c
index c5a4478..e19232f 100644
--- a/arch/powerpc/kvm/book3s.c
+++ b/arch/powerpc/kvm/book3s.c
@@ -529,6 +529,15 @@ int kvm_vcpu_ioctl_get_one_reg(struct kvm_vcpu *vcpu, 
struct kvm_one_reg *reg)
                        val = get_reg_val(reg->id, vcpu->arch.vscr.u[3]);
                        break;
 #endif /* CONFIG_ALTIVEC */
+#ifdef CONFIG_PPC_BOOK3S_64
+               case KVM_REG_PPC_ICP_STATE:
+                       if (!vcpu->arch.icp) {
+                               r = -ENXIO;
+                               break;
+                       }
+                       val = get_reg_val(reg->id, kvmppc_xics_get_icp(vcpu));
+                       break;
+#endif
                default:
                        r = -EINVAL;
                        break;
@@ -591,6 +600,15 @@ int kvm_vcpu_ioctl_set_one_reg(struct kvm_vcpu *vcpu, 
struct kvm_one_reg *reg)
                        vcpu->arch.vscr.u[3] = set_reg_val(reg->id, val);
                        break;
 #endif /* CONFIG_ALTIVEC */
+#ifdef CONFIG_PPC_BOOK3S_64
+               case KVM_REG_PPC_ICP_STATE:
+                       if (!vcpu->arch.icp) {
+                               r = -ENXIO;
+                               break;
+                       }
+                       r = kvmppc_xics_set_icp(vcpu, set_reg_val(reg->id, 
val));
+                       break;
+#endif
                default:
                        r = -EINVAL;
                        break;
diff --git a/arch/powerpc/kvm/book3s_xics.c b/arch/powerpc/kvm/book3s_xics.c
index 7b29cb8..8314cd9 100644
--- a/arch/powerpc/kvm/book3s_xics.c
+++ b/arch/powerpc/kvm/book3s_xics.c
@@ -976,6 +976,96 @@ void kvmppc_xics_free(struct kvm *kvm)
        kfree(xics);
 }
 
+u64 kvmppc_xics_get_icp(struct kvm_vcpu *vcpu)
+{
+       struct kvmppc_icp *icp = vcpu->arch.icp;
+       union kvmppc_icp_state state;
+
+       if (!icp)
+               return 0;
+       state = icp->state;
+       return ((u64)state.cppr << KVM_REG_PPC_ICP_CPPR_SHIFT) |
+               ((u64)state.xisr << KVM_REG_PPC_ICP_XISR_SHIFT) |
+               ((u64)state.mfrr << KVM_REG_PPC_ICP_MFRR_SHIFT) |
+               ((u64)state.pending_pri << KVM_REG_PPC_ICP_PPRI_SHIFT);
+}
+
+int kvmppc_xics_set_icp(struct kvm_vcpu *vcpu, u64 icpval)
+{
+       struct kvmppc_icp *icp = vcpu->arch.icp;
+       struct kvmppc_xics *xics = vcpu->kvm->arch.xics;
+       union kvmppc_icp_state old_state, new_state;
+       struct kvmppc_ics *ics;
+       u8 cppr, mfrr, pending_pri;
+       u32 xisr;
+       u16 src;
+       bool resend;
+
+       if (!icp || !xics)
+               return -ENOENT;
+
+       cppr = icpval >> KVM_REG_PPC_ICP_CPPR_SHIFT;
+       xisr = (icpval >> KVM_REG_PPC_ICP_XISR_SHIFT) &
+               KVM_REG_PPC_ICP_XISR_MASK;
+       mfrr = icpval >> KVM_REG_PPC_ICP_MFRR_SHIFT;
+       pending_pri = icpval >> KVM_REG_PPC_ICP_PPRI_SHIFT;
+
+       /* Require the new state to be internally consistent */
+       if (xisr == 0) {
+               if (pending_pri != 0xff)
+                       return -EINVAL;
+       } else if (xisr == XICS_IPI) {
+               if (pending_pri != mfrr || pending_pri >= cppr)
+                       return -EINVAL;
+       } else {
+               if (pending_pri >= mfrr || pending_pri >= cppr)
+                       return -EINVAL;
+               ics = kvmppc_xics_find_ics(xics, xisr, &src);
+               if (!ics)
+                       return -EINVAL;
+       }
+
+       new_state.raw = 0;
+       new_state.cppr = cppr;
+       new_state.xisr = xisr;
+       new_state.mfrr = mfrr;
+       new_state.pending_pri = pending_pri;
+
+       /*
+        * Deassert the CPU interrupt request.
+        * icp_try_update will reassert it if necessary.
+        */
+       kvmppc_book3s_dequeue_irqprio(icp->vcpu,
+                                     BOOK3S_INTERRUPT_EXTERNAL_LEVEL);
+
+       /*
+        * Note that if we displace an interrupt from old_state.xisr,
+        * we don't mark it as rejected.  We expect userspace to set
+        * the state of the interrupt sources to be consistent with
+        * the ICP states (either before or afterwards, which doesn't
+        * matter).  We do handle resends due to CPPR becoming less
+        * favoured because that is necessary to end up with a
+        * consistent state in the situation where userspace restores
+        * the ICS states before the ICP states.
+        */
+       do {
+               old_state = ACCESS_ONCE(icp->state);
+
+               if (new_state.mfrr <= old_state.mfrr) {
+                       resend = false;
+                       new_state.need_resend = old_state.need_resend;
+               } else {
+                       resend = old_state.need_resend;
+                       new_state.need_resend = 0;
+               }
+       } while (!icp_try_update(icp, old_state, new_state, false));
+
+       if (resend)
+               icp_check_resend(xics, icp);
+
+       return 0;
+}
+
 /* -- ioctls -- */
 
 static int kvm_vm_ioctl_create_icp(struct kvm *kvm,
-- 
1.7.10.4

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