On Mon, Dec 24, 2012 at 11:53:37PM +0000, Zhang, Yang Z wrote:
> Gleb Natapov wrote on 2012-12-24:
> > On Mon, Dec 24, 2012 at 02:35:35AM +0000, Zhang, Yang Z wrote:
> >> Zhang, Yang Z wrote on 2012-12-24:
> >>> Gleb Natapov wrote on 2012-12-20:
> >>>> On Mon, Dec 17, 2012 at 01:30:50PM +0800, Yang Zhang wrote:
> >>>>> basically to benefit from apicv, we need clear MSR bitmap for
> >>>>> corresponding x2apic MSRs:
> >>>>> 0x800 - 0x8ff: no read intercept for apicv register virtualization
> >>>>> TPR,EOI,SELF-IPI: no write intercept for virtual interrupt delivery
> >>>> We do not set "Virtualize x2APIC mode" bit in secondary execution
> >>>> control. If I read the spec correctly without that those MSR read/writes
> >>>> will go straight to physical local APIC.
> >>> Right. Now it cannot get benefit, but we may enable it in future and
> >>> then we can benefit from it.
> > Without enabling it you cannot disable MSR intercept for x2apic MSRs.
> >
> >> how about to add the following check:
> >> if (apicv_enabled && virtual_x2apic_enabled)
> >> clear_msr();
> >>
> > I do not understand what do you mean here.
> In this patch, it will clear MSR bitmap(0x800 -0x8ff) when apicv enabled. As
> you said, since kvm doesn't set "virtualize x2apic mode", APIC register
> virtualization never take effect. So we need to clear MSR bitmap only when
> apicv enabled and virtualize x2apic mode set.
>
But currently it is never set.
--
Gleb.
--
To unsubscribe from this list: send the line "unsubscribe kvm" in
the body of a message to [email protected]
More majordomo info at http://vger.kernel.org/majordomo-info.html
