Signed-off: Vadim Rozenfeld <[email protected]>

The following patch allows to activate a partition reference 
time enlightenment that is based on the host platform's support 
for an Invariant Time Stamp Counter (iTSC).
NOTE: This code will survive migration due to lack of VM stop/resume
handlers.

---
 arch/x86/include/uapi/asm/hyperv.h | 10 ++++++++++
 arch/x86/kvm/x86.c                 | 18 +++++++++++++-----
 include/uapi/linux/kvm.h           |  1 +
 3 files changed, 24 insertions(+), 5 deletions(-)

diff --git a/arch/x86/include/uapi/asm/hyperv.h 
b/arch/x86/include/uapi/asm/hyperv.h
index 9711819..2d9e666 100644
--- a/arch/x86/include/uapi/asm/hyperv.h
+++ b/arch/x86/include/uapi/asm/hyperv.h
@@ -182,6 +182,9 @@
 #define HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_MASK       \
                (~((1ull << HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT) - 1))
 
+#define HV_X64_MSR_TSC_REFERENCE_ENABLE                        0x00000001
+#define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT         12
+
 #define HV_PROCESSOR_POWER_STATE_C0            0
 #define HV_PROCESSOR_POWER_STATE_C1            1
 #define HV_PROCESSOR_POWER_STATE_C2            2
@@ -194,4 +197,11 @@
 #define HV_STATUS_INVALID_ALIGNMENT            4
 #define HV_STATUS_INSUFFICIENT_BUFFERS         19
 
+typedef struct _HV_REFERENCE_TSC_PAGE {
+       uint32_t TscSequence;
+       uint32_t Rserved1;
+       uint64_t TscScale;
+       int64_t  TscOffset;
+} HV_REFERENCE_TSC_PAGE, * PHV_REFERENCE_TSC_PAGE;
+
 #endif
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 1a4036d..5788e8f 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -1809,14 +1809,21 @@ static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 
msr, u64 data)
                break;
        }
        case HV_X64_MSR_REFERENCE_TSC: {
-               u64 gfn;
                unsigned long addr;
-               u32 tsc_ref;
-               gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
-               addr = gfn_to_hva(kvm, gfn);
+               HV_REFERENCE_TSC_PAGE tsc_ref;
+               tsc_ref.TscSequence =
+                       boot_cpu_has(X86_FEATURE_CONSTANT_TSC) ? 1 : 0;
+               tsc_ref.TscScale =
+                       ((10000LL << 32) /vcpu->arch.virtual_tsc_khz) << 32;
+               tsc_ref.TscOffset = 0;
+               if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE)) {
+                       kvm->arch.hv_tsc_page = data;
+                       break;
+               }
+               addr = gfn_to_hva(vcpu->kvm, data >>
+                       HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT);
                if (kvm_is_error_hva(addr))
                        return 1;
-               tsc_ref = 0;
                if(__copy_to_user((void __user *)addr, &tsc_ref, 
sizeof(tsc_ref)))
                        return 1;
                kvm->arch.hv_tsc_page = data;
@@ -2553,6 +2560,7 @@ int kvm_dev_ioctl_check_extension(long ext)
        case KVM_CAP_HYPERV:
        case KVM_CAP_HYPERV_VAPIC:
        case KVM_CAP_HYPERV_SPIN:
+       case KVM_CAP_HYPERV_TSC:
        case KVM_CAP_PCI_SEGMENT:
        case KVM_CAP_DEBUGREGS:
        case KVM_CAP_X86_ROBUST_SINGLESTEP:
diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
index a5c86fc..8eff540 100644
--- a/include/uapi/linux/kvm.h
+++ b/include/uapi/linux/kvm.h
@@ -666,6 +666,7 @@ struct kvm_ppc_smmu_info {
 #define KVM_CAP_IRQ_MPIC 90
 #define KVM_CAP_PPC_RTAS 91
 #define KVM_CAP_IRQ_XICS 92
+#define KVM_CAP_HYPERV_TSC 93
 
 #ifdef KVM_CAP_IRQ_ROUTING
 
-- 
1.8.1.2

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