Hi Peter, 2017-06-23 18:18 GMT+08:00, Peter Maydell <[email protected]>: > On 23 June 2017 at 10:38, James Morse <[email protected]> wrote: >> So the v8 ARM-ARM has two ways of indicating an external abort, KVM tests >> bit 9 >> The v7 ARM-ARm has a '{D,I}FSR.ExT' bit, which I think is equivalent. Its >> described as: >>> An implementation can use the DFSR.ExT and IFSR.ExT bits to provide more >>> information about external aborts. > > For instance, the Cortex-A15 TRM documents that it uses the ExT bit > to distinguish AXI DECERR (decode error, ExT==0) and SLVERR (slave > error, ExT==1) abort responses. > >>> This is what the v8 version must mean with its >>> External abort type. This bit can provide an IMPLEMENTATION DEFINED >>> classification of External aborts. >> >> Which I read as IMP-DEF classification 'as external', as opposed to your >> reading >> as an extra IMP-DEF classification for external aborts. > > I think gengdongjiu's reading is correct here: if this > is an external abort then you can find out more info about > exactly what kind of EA it is by looking at this bit, but > you have to look at the FSC bits to be sure it is an EA first. > > The Cortex-A53 TRM documents that it uses the same SLVERR-vs-DECERR > semantics for DFSR.ExT as the A15. It doesn't say so but it wouldn't > be very surprising if its usage of ESR_ELx.EA was the same. Arm Cortex-A53 may use this EA bit for AXI DECERR (decode error, ExT==0) and SLVERR abort. but not all CPUs have the same semantics. For example, Huawei's designed armv8.2 CPU is not that semantics
> > thanks > -- PMM > _______________________________________________ > kvmarm mailing list > [email protected] > https://lists.cs.columbia.edu/mailman/listinfo/kvmarm > _______________________________________________ kvmarm mailing list [email protected] https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
