This patch is used for GICv2 on GICv3.
About GICV_APRn hardware register access,the SPEC says:
When System register access is enabled for EL2, these registers access
ICH_AP1Rn_EL2, and all active priorities for virtual machines are held
in ICH_AP1Rn_EL2 regardless of interrupt group.
For GICv3 hardware, we access the active priorities from ICH_AP1Rn_EL2
in this scene.
Aiming at the userspace access the undefined APR registers which the
hardwate doesn't implement, it will be treates ad raz/wi.
Signed-off-by: wanghaibin <wanghaibin.w...@huawei.com>
---
virt/kvm/arm/vgic/vgic-mmio.c | 16 +++++++++++++--
virt/kvm/arm/vgic/vgic-v3.c | 48 +++++++++++++++++++++++++++++++++++++++++++
virt/kvm/arm/vgic/vgic.h | 2 ++
3 files changed, 64 insertions(+), 2 deletions(-)
diff --git a/virt/kvm/arm/vgic/vgic-mmio.c b/virt/kvm/arm/vgic/vgic-mmio.c
index 80261b7..738d800 100644
--- a/virt/kvm/arm/vgic/vgic-mmio.c
+++ b/virt/kvm/arm/vgic/vgic-mmio.c
@@ -494,14 +494,26 @@ static int match_region(const void *key, const void *elt)
void vgic_set_apr(struct kvm_vcpu *vcpu, u32 idx, u32 val)
{
- if (kvm_vgic_global_state.type == VGIC_V2)
+ u32 vgic_model = vcpu->kvm->arch.vgic.vgic_model;
+
+ if (kvm_vgic_global_state.type == VGIC_V2) {
vgic_v2_set_apr(vcpu, idx, val);
+ } else {
+ if (vgic_model == KVM_DEV_TYPE_ARM_VGIC_V2)
+ vgic_v3_set_apr(vcpu, 1, idx, val);
+ }
}
u32 vgic_get_apr(struct kvm_vcpu *vcpu, u32 idx)
{
- if (kvm_vgic_global_state.type == VGIC_V2)
+ u32 vgic_model = vcpu->kvm->arch.vgic.vgic_model;
+
+ if (kvm_vgic_global_state.type == VGIC_V2) {
return vgic_v2_get_apr(vcpu, idx);
+ } else {
+ if (vgic_model == KVM_DEV_TYPE_ARM_VGIC_V2)
+ return vgic_v3_get_apr(vcpu, 1, idx);
+ }
return 0;
}
diff --git a/virt/kvm/arm/vgic/vgic-v3.c b/virt/kvm/arm/vgic/vgic-v3.c
index 96ea597..2625dfd 100644
--- a/virt/kvm/arm/vgic/vgic-v3.c
+++ b/virt/kvm/arm/vgic/vgic-v3.c
@@ -160,6 +160,54 @@ void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr)
vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = 0;
}
+static bool vgic_v3_apr_access_valid(struct kvm_vcpu *vcpu, u32 idx)
+{
+ struct vgic_cpu *vgic_v3_cpu = &vcpu->arch.vgic_cpu;
+
+ if (idx > 3)
+ return false;
+
+ switch (vgic_v3_cpu->num_pri_bits) {
+ case 7:
+ return true;
+ case 6:
+ if (idx > 1)
+ return false;
+ break;
+ default:
+ if (idx > 0)
+ return false;
+ }
+
+ return true;
+}
+
+void vgic_v3_set_apr(struct kvm_vcpu *vcpu, u8 group, u32 idx, u32 val)
+{
+ struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
+
+ if (!vgic_v3_apr_access_valid(vcpu, idx))
+ return;
+
+ if (group)
+ cpu_if->vgic_ap1r[idx] = val;
+ else
+ cpu_if->vgic_ap0r[idx] = val;
+}
+
+u32 vgic_v3_get_apr(struct kvm_vcpu *vcpu, u8 group, u32 idx)
+{
+ struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
+
+ if (!vgic_v3_apr_access_valid(vcpu, idx))
+ return 0;
+
+ if (group)
+ return cpu_if->vgic_ap1r[idx];
+ else
+ return cpu_if->vgic_ap0r[idx];
+}
+
void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
{
struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
diff --git a/virt/kvm/arm/vgic/vgic.h b/virt/kvm/arm/vgic/vgic.h
index 441ded7..19b0f8b 100644
--- a/virt/kvm/arm/vgic/vgic.h
+++ b/virt/kvm/arm/vgic/vgic.h
@@ -181,6 +181,8 @@ static inline void vgic_get_irq_kref(struct vgic_irq *irq)
void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr);
void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr);
void vgic_v3_set_underflow(struct kvm_vcpu *vcpu);
+void vgic_v3_set_apr(struct kvm_vcpu *vcpu, u8 group, u32 idx, u32 val);
+u32 vgic_v3_get_apr(struct kvm_vcpu *vcpu, u8 group, u32 idx);
void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
void vgic_v3_enable(struct kvm_vcpu *vcpu);
--
1.8.3.1
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