On 02/07/18 16:02, Marc Zyngier wrote:
> This small series makes use of features recently introduced in the
> ARMv8 architecture to relax the cache maintenance operations on CPUs
> that implement these features.
>
> FWB is the most important one. It allows stage-2 to enforce the
> cacheability of memory, no matter what the guest says. It also
> mandates that the whole machine is cache coherent (no non-coherent
> I/O), meaning we can drop a whole class of cache maintenance
> operations.
>
> FWB also has the same effect as CTR_EL0.IDC being set, and when
> combined with CTR_EL0.DIC allows the removal of all cache maintenance
> and tracking of pages being executed.
>
> We also take the opportunity to drop a few useless CMOs that were
> applied to the HYP page tables, but that were never necessary. This
> ended up requiring quite a few changes in out page table accessors so
> that they get consistent barriers. These barriers are a bit on the
> heavy side, and could be further optimized, although that's probably
> for a different patch series
>
> Unless someone screams now, I plan to apply this to kvmarm/next
> shortly.
Now applied to queue.
M.
--
Jazz is not dead. It just smells funny...
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