Hi Marc, On 06/12/2018 17:31, Marc Zyngier wrote: > Early Cortex-A76 suffer from an erratum that can result in invalid > TLBs when the CPU speculatively executes an AT instruction in the > middle of a guest world switch, while the guest virtual memory > configuration is in an inconsistent state. > > We handle this issue by mandating the use of VHE and making sure that > the guest context is fully installed before switching HCR_EL2.TGE to > zero. This ensures that a speculated AT instruction is either executed > on the host context (TGE set) or the guest context (TGE clear), and > that there is no intermediate state. > > There is some additional complexity in the TLB invalidation code, > where we most make sure that a speculated AT instruction cannot mess > the stage-1 TLBs.
For the series: Reviewed-by: James Morse <[email protected]> Thanks, James _______________________________________________ kvmarm mailing list [email protected] https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
