On Sun, Sep 08, 2019 at 07:52:55AM +0800, Guo Ren wrote: > On Mon, Jun 24, 2019 at 6:40 PM Will Deacon <[email protected]> wrote: > > > I'll keep my system use the same ASID for SMP + IOMMU :P > > > > You will want a separate allocator for that: > > > > https://lkml.kernel.org/r/[email protected] > > Yes, it is hard to maintain ASID between IOMMU and CPUMMU or different > system, because it's difficult to synchronize the IO_ASID when the CPU > ASID is rollover. > But we could still use hardware broadcast TLB invalidation instruction > to uniformly manage the ASID and IO_ASID, or OTHER_ASID in our IOMMU.
That's probably a bad idea, because you'll likely stall execution on the CPU until the IOTLB has completed invalidation. In the case of ATS, I think an endpoint ATC is permitted to take over a minute to respond. In reality, I suspect the worst you'll ever see would be in the msec range, but that's still an unacceptable period of time to hold a CPU. > Welcome to join our disscusion: > "Introduce an implementation of IOMMU in linux-riscv" > 9 Sep 2019, 10:45 Jade-room-I&II (Corinthia Hotel Lisbon) RISC-V MC I attended this session, but it unfortunately raised many more questions than it answered. Will _______________________________________________ kvmarm mailing list [email protected] https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
