Variable argument macros frequently depend on floating point registers. Indeed we needed to enable the VFP for arm64 since its introduction in order to use printf and the like. Somehow we didn't need to do that for arm32 until recently when compiling with GCC 9.
Signed-off-by: Andrew Jones <[email protected]> --- v2: Added '-mfpu=vfp' cflag to deal with older compilers CC'ing Thomas because I think he had to workaround travis tests failing due to this issue once. Maybe travis can now be un-worked-around? arm/Makefile.arm | 2 +- arm/cstart.S | 14 +++++++++++++- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/arm/Makefile.arm b/arm/Makefile.arm index 43b4be1e05ee..d379a2800749 100644 --- a/arm/Makefile.arm +++ b/arm/Makefile.arm @@ -5,7 +5,7 @@ # bits = 32 ldarch = elf32-littlearm -machine = -marm +machine = -marm -mfpu=vfp # stack.o relies on frame pointers. KEEP_FRAME_POINTER := y diff --git a/arm/cstart.S b/arm/cstart.S index 114726feab82..bc6219d8a3ee 100644 --- a/arm/cstart.S +++ b/arm/cstart.S @@ -50,10 +50,11 @@ start: mov r0, r2 push {r0-r1} - /* set up vector table and mode stacks */ + /* set up vector table, mode stacks, and enable the VFP */ mov r0, lr @ lr is stack top (see above), @ which is the exception stacks base bl exceptions_init + bl enable_vfp /* complete setup */ pop {r0-r1} @@ -100,6 +101,16 @@ exceptions_init: isb mov pc, lr +enable_vfp: + /* Enable full access to CP10 and CP11: */ + mov r0, #(3 << 22 | 3 << 20) + mcr p15, 0, r0, c1, c0, 2 + isb + /* Set the FPEXC.EN bit to enable Advanced SIMD and VFP: */ + mov r0, #(1 << 30) + vmsr fpexc, r0 + mov pc, lr + .text .global get_mmu_off @@ -130,6 +141,7 @@ secondary_entry: ldr r0, [r1] mov sp, r0 bl exceptions_init + bl enable_vfp /* finish init in C code */ bl secondary_cinit -- 2.21.0 _______________________________________________ kvmarm mailing list [email protected] https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
