From: Sudeep Holla <sudeep.ho...@arm.com>
It's not entirely clear for the binding document that the only way to
express ARM SPE affined to a subset of CPUs on a heterogeneous systems
is through the use of PPI partitions available in the interrupt
controller bindings.
Let's make it clear.
Signed-off-by: Sudeep Holla <sudeep.ho...@arm.com>
Signed-off-by: Andrew Murray <andrew.mur...@arm.com>
---
Documentation/devicetree/bindings/arm/spe-pmu.txt | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/spe-pmu.txt
b/Documentation/devicetree/bindings/arm/spe-pmu.txt
index 93372f2a7df9..4f4815800f6e 100644
--- a/Documentation/devicetree/bindings/arm/spe-pmu.txt
+++ b/Documentation/devicetree/bindings/arm/spe-pmu.txt
@@ -9,8 +9,9 @@ performance sample data using an in-memory trace buffer.
"arm,statistical-profiling-extension-v1"
- interrupts : Exactly 1 PPI must be listed. For heterogeneous systems where
- SPE is only supported on a subset of the CPUs, please consult
- the arm,gic-v3 binding for details on describing a PPI partition.
+ SPE is only supported on a subset of the CPUs, a PPI partition
+ described in the arm,gic-v3 binding must be used to describe
+ the set of CPUs this interrupt is affine to.
** Example:
--
2.21.0
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