Depending on the HCR_EL2.{E2H,TGE} values, SCTLR_EL2 has different
RES0/RES1 constraints.

Let's handle that.

Signed-off-by: Marc Zyngier <m...@kernel.org>
---
 arch/arm64/kvm/sys_regs.c | 33 ++++++++++++++++++++++++++++++++-
 1 file changed, 32 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index c62080d7742c..121b3f28cae2 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -443,6 +443,37 @@ static bool access_vbar_el1(struct kvm_vcpu *vcpu,
        return access_rw(vcpu, p, r);
 }
 
+static bool access_sctlr_el2(struct kvm_vcpu *vcpu,
+                            struct sys_reg_params *p,
+                            const struct sys_reg_desc *r)
+{
+       if (el12_reg(p) && forward_nv_traps(vcpu))
+               return false;
+
+       if (p->is_write) {
+               u64 val = p->regval;
+
+               if (vcpu_el2_e2h_is_set(vcpu) && vcpu_el2_tge_is_set(vcpu)) {
+                       val &= ~(GENMASK_ULL(63,45) | GENMASK_ULL(34, 32) |
+                                BIT_ULL(17));
+                       val |=  SCTLR_EL1_RES1;
+               } else {
+                       val &= ~(GENMASK_ULL(63,45) | BIT_ULL(42) |
+                                GENMASK_ULL(39, 38) | GENMASK_ULL(35, 32) |
+                                BIT_ULL(26) | BIT_ULL(24) | BIT_ULL(20) |
+                                BIT_ULL(17) | GENMASK_ULL(15, 14) |
+                                GENMASK(10, 7));
+                       val |=  SCTLR_EL2_RES1;
+               }
+
+               vcpu_write_sys_reg(vcpu, val, r->reg);
+       } else {
+               p->regval = vcpu_read_sys_reg(vcpu, r->reg);
+       }
+
+       return true;
+}
+
 /*
  * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
  */
@@ -2254,7 +2285,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
        { SYS_DESC(SYS_VPIDR_EL2), access_rw, reset_vpidr, VPIDR_EL2 },
        { SYS_DESC(SYS_VMPIDR_EL2), access_rw, reset_vmpidr, VMPIDR_EL2 },
 
-       { SYS_DESC(SYS_SCTLR_EL2), access_rw, reset_val, SCTLR_EL2, 0 },
+       { SYS_DESC(SYS_SCTLR_EL2), access_sctlr_el2, reset_val, SCTLR_EL2, 
SCTLR_EL2_RES1 },
        { SYS_DESC(SYS_ACTLR_EL2), access_rw, reset_val, ACTLR_EL2, 0 },
        { SYS_DESC(SYS_HCR_EL2), access_rw, reset_val, HCR_EL2, 0 },
        { SYS_DESC(SYS_MDCR_EL2), access_rw, reset_val, MDCR_EL2, 0 },
-- 
2.20.1

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