Hi Marc, On 3/4/20 9:33 PM, Marc Zyngier wrote: > To allow the direct injection of SGIs into a guest, the GICv4.1 > architecture has to sacrifice the Active state so that SGIs look > a lot like LPIs (they are injected by the same mechanism). > > In order not to break existing software, the architecture gives > offers guests OSs the choice: SGIs with or without an active nit gives offers > state. It is the hypervisors duty to honor the guest's choice. > > For this, the architecture offers a discovery bit indicating whether > the GIC supports GICv4.1 SGIs (GICD_TYPER2.nASSGIcap), and another > bit indicating whether the guest wants Active-less SGIs or not > (controlled by GICD_CTLR.nASSGIreq). > > A hypervisor not supporting GICv4.1 SGIs would leave nASSGIcap > clear, and a guest not knowing about GICv4.1 SGIs (or definitely > wanting an Active state) would leave nASSGIreq clear (both being > thankfully backward compatible with older revisions of the GIC). > > Since Linux is perfectly happy without an active state on SGIs, > inform the hypervisor that we'll use that if offered. > > Signed-off-by: Marc Zyngier <[email protected]> > Reviewed-by: Zenghui Yu <[email protected]> > --- > drivers/irqchip/irq-gic-v3.c | 10 ++++++++-- > include/linux/irqchip/arm-gic-v3.h | 2 ++ > 2 files changed, 10 insertions(+), 2 deletions(-) > > diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c > index cd76435c4a31..73e87e176d76 100644 > --- a/drivers/irqchip/irq-gic-v3.c > +++ b/drivers/irqchip/irq-gic-v3.c > @@ -724,6 +724,7 @@ static void __init gic_dist_init(void) > unsigned int i; > u64 affinity; > void __iomem *base = gic_data.dist_base; > + u32 val; > > /* Disable the distributor */ > writel_relaxed(0, base + GICD_CTLR); > @@ -756,9 +757,14 @@ static void __init gic_dist_init(void) > /* Now do the common stuff, and wait for the distributor to drain */ > gic_dist_config(base, GIC_LINE_NR, gic_dist_wait_for_rwp); > > + val = GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1; > + if (gic_data.rdists.gicd_typer2 & GICD_TYPER2_nASSGIcap) { > + pr_info("Enabling SGIs without active state\n"); > + val |= GICD_CTLR_nASSGIreq; > + } > + > /* Enable distributor with ARE, Group1 */ > - writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | > GICD_CTLR_ENABLE_G1, > - base + GICD_CTLR); > + writel_relaxed(val, base + GICD_CTLR); > > /* > * Set all global interrupts to the boot CPU only. ARE must be > diff --git a/include/linux/irqchip/arm-gic-v3.h > b/include/linux/irqchip/arm-gic-v3.h > index 83439bfb6c5b..c29a02678a6f 100644 > --- a/include/linux/irqchip/arm-gic-v3.h > +++ b/include/linux/irqchip/arm-gic-v3.h > @@ -57,6 +57,7 @@ > #define GICD_SPENDSGIR 0x0F20 > > #define GICD_CTLR_RWP (1U << 31) > +#define GICD_CTLR_nASSGIreq (1U << 8) I am not able to find this bit in Arm IHI 0069F (ID022020) same for the bit in GICD_TYPER. Do we still miss part of the spec?
Thanks Eric > #define GICD_CTLR_DS (1U << 6) > #define GICD_CTLR_ARE_NS (1U << 4) > #define GICD_CTLR_ENABLE_G1A (1U << 1) > @@ -90,6 +91,7 @@ > #define GICD_TYPER_ESPIS(typer) > \ > (((typer) & GICD_TYPER_ESPI) ? GICD_TYPER_SPIS((typer) >> 27) : 0) > > +#define GICD_TYPER2_nASSGIcap (1U << 8) > #define GICD_TYPER2_VIL (1U << 7) > #define GICD_TYPER2_VID GENMASK(4, 0) > > _______________________________________________ kvmarm mailing list [email protected] https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
