On Tue, Jan 28, 2020 at 06:09:04PM +0530, Anshuman Khandual wrote: > This adds basic building blocks required for ID_PFR2 CPU register which > provides information about the AArch32 programmers model which must be > interpreted along with ID_PFR0 and ID_PFR1 CPU registers. > > Cc: Catalin Marinas <[email protected]> > Cc: Will Deacon <[email protected]> > Cc: Marc Zyngier <[email protected]> > Cc: James Morse <[email protected]> > Cc: Suzuki K Poulose <[email protected]> > Cc: Mark Rutland <[email protected]> > Cc: [email protected] > Cc: [email protected] > Signed-off-by: Anshuman Khandual <[email protected]> > --- > arch/arm64/include/asm/cpu.h | 1 + > arch/arm64/include/asm/sysreg.h | 4 ++++ > arch/arm64/kernel/cpufeature.c | 11 +++++++++++ > arch/arm64/kernel/cpuinfo.c | 1 + > arch/arm64/kvm/sys_regs.c | 2 +- > 5 files changed, 18 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h > index b4a40535a3d8..464e828a994d 100644 > --- a/arch/arm64/include/asm/cpu.h > +++ b/arch/arm64/include/asm/cpu.h > @@ -46,6 +46,7 @@ struct cpuinfo_arm64 { > u32 reg_id_mmfr3; > u32 reg_id_pfr0; > u32 reg_id_pfr1; > + u32 reg_id_pfr2; > > u32 reg_mvfr0; > u32 reg_mvfr1; > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index b91570ff9db1..054aab7ebf1b 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -151,6 +151,7 @@ > #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0) > #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1) > #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2) > +#define SYS_ID_PFR2_EL1 sys_reg(3, 0, 0, 3, 4) > > #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0) > #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1) > @@ -717,6 +718,9 @@ > #define ID_ISAR6_DP_SHIFT 4 > #define ID_ISAR6_JSCVT_SHIFT 0 > > +#define ID_PFR2_SSBS_SHIFT 4 > +#define ID_PFR2_CSV3_SHIFT 0 > + > #define MVFR0_FPROUND_SHIFT 28 > #define MVFR0_FPSHVEC_SHIFT 24 > #define MVFR0_FPSQRT_SHIFT 20 > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index 0b6715625cf6..c1e837fc8f97 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -348,6 +348,12 @@ static const struct arm64_ftr_bits ftr_id_pfr0[] = { > ARM64_FTR_END, > }; > > +static const struct arm64_ftr_bits ftr_id_pfr2[] = { > + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, > ID_PFR2_SSBS_SHIFT, 4, 0), > + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, > ID_PFR2_CSV3_SHIFT, 4, 0),
Why is CSV3 strict here, but not when we see if in aa64pfr0? I think it should be non-strict in both cases. Will _______________________________________________ kvmarm mailing list [email protected] https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
