On Fri, 05 Mar 2021 19:07:09 +0000,
Catalin Marinas <[email protected]> wrote:
>
> On Wed, Mar 03, 2021 at 04:45:05PM +0000, Marc Zyngier wrote:
> > It recently became apparent that the ARMv8 architecture has interesting
> > rules regarding attributes being used when fetching instructions
> > if the MMU is off at Stage-1.
> >
> > In this situation, the CPU is allowed to fetch from the PoC and
> > allocate into the I-cache (unless the memory is mapped with
> > the XN attribute at Stage-2).
>
> Digging through the ARM ARM is hard. Do we have this behaviour with FWB
> as well?
The ARM ARM doesn't seem to mention FWB at all when it comes to
instruction fetch, which is sort of expected as it only covers the
D-side. I *think* we could sidestep this when CTR_EL0.DIC is set
though, as the I-side would then snoop the D-side.
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
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