On Tue, 10 Aug 2021 09:59:42 +0530, Anshuman Khandual wrote:
> Streamline the Stage-2 TGRAN value extraction from ID_AA64MMFR0 register by
> adding a page size agnostic ID_AA64MMFR0_TGRAN_2_SHIFT. This is similar to
> the existing Stage-1 TGRAN shift i.e ID_AA64MMFR0_TGRAN_SHIFT.
Applied to kvm-arm64/misc-5.15, thanks!
[1/1] arm64/mm: Define ID_AA64MMFR0_TGRAN_2_SHIFT
commit: 9efb41493ddfb19c7b3d0a21d68be6279520144f
Cheers,
M.
--
Without deviation from the norm, progress is not possible.
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