On Tue, Mar 01, 2022 at 05:56:41PM -0500, Qian Cai wrote: > On Mon, Feb 07, 2022 at 03:20:32PM +0000, Mark Brown wrote: > > Since all the fields in the main ID registers are 4 bits wide we have up > > until now not bothered specifying the width in the code. Since we now
> Do we leave this one alone on purpose? > .desc = "GIC system register CPU interface", > .capability = ARM64_HAS_SYSREG_GIC_CPUIF, > .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, > .matches = has_useable_gicv3_cpuif, > .sys_reg = SYS_ID_AA64PFR0_EL1, > .field_pos = ID_AA64PFR0_GIC_SHIFT, > .sign = FTR_UNSIGNED, > .min_field_value = 1, No, that's just an oversight.
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