Hi Michael, On Mon Jun 05, 2023 at 18:39:25 +0200, Michael Willig wrote: > I would like to try Fiasco/L4Re for a Mixed-Critical Xilinx UltraScale+ > FPGA-MPSoC (the hardware accelerators on the FPGA should be > virtualized/isolated for mixed-critical applications) Is there somewhere an > example (or at least starting point) of an ARM Trustzone configuration of a > Normal World VM and Secure World VM (with UVMM/Fiasco as hypervisor that > also takes care of the ARM Trustzone configuration)?
This SoC does not support running VMs on the TZ side. What about just ignoring the TZ side? Is there any benefit separating workloads between normal and TZ side? Adam _______________________________________________ l4-hackers mailing list l4-hackers@os.inf.tu-dresden.de https://os.inf.tu-dresden.de/mailman/listinfo/l4-hackers
