On Mon, 2005-10-10 at 03:12 +0200, [EMAIL PROTECTED] wrote: > Hi, > > > The one thing that makes me put these in-kernel heaps on the "deferred" > > list rather than the "forget" list is my concern that hardware context > > switch performance is getting steadily worse, and that microkernel > > designs may have to compromise purity to remain competitive. This is > > disturbing, but it may be inevitable. > > Is it really getting worse? I read that someone managed to bring L4 IPC > on Itanium down to 36 cycles. In view of the *theoretical* scalability > of the different processors, this seems about similar to the 121 cycles > L4 claimed on Pentium 1.
There exist processors that do context switch perfectly well. Even so, the IA32 will remain the most important target for a long time, and on that platform things are getting steadily worse. shap _______________________________________________ L4-hurd mailing list [email protected] http://lists.gnu.org/mailman/listinfo/l4-hurd
