On 5/9/07, Bart Smaalders <bart.smaalders at sun.com> wrote: > > Thomas De Schampheleire wrote: > > > > On 5/9/07, *Bart Smaalders* <bart.smaalders at sun.com > > <mailto:bart.smaalders at sun.com>> wrote: > > > > Thomas De Schampheleire wrote: > > > I will be implementing a power management strategy which will > > shutdown > > > cpu's, so therefore in my situation it will have something to do > with > > > power management. > > > > > > What do you exactly mean with "halt"? I suppose you are talking > about > > > gating the clock, right? > > > > > > > Note that this routine gets called in the idle loop: > > > > > http://cvs.opensolaris.org/source/xref/onnv/onnv-gate/usr/src/uts/i86pc/os/mp_machdep.c#255 > > > > > > Hi, > > > > I'm using SPARC, but nevertheless it is interesting to see that halting > > is already done in x86. I do not immediately find a reference to what > > halting exactly is, but I do suppose it means clock gating. That is what > > I generally understand under halting, and is indeed acceptable to do > > from an idle loop because the penalty to get out of the halt is quite > small. > > > > Here's what's being done on sun4v: > > > http://cvs.opensolaris.org/source/xref/onnv/onnv-gate/usr/src/uts/sun4v/os/mach_startup.c#85 > > > > I would like to go a step further and put the cpu in lower power states > > and eventually shut it down. Do you know whether a similar thing is > > already done or supported in the x86 code? > > > > This is not yet being done; the work is close to finished from what I > understand and should soon go into opensolaris. I believe the approach > that is being used is that the cpu will run slower and slower as the > load drops. Whether or not the cpu is halted is orthogonal to its > power level....
Do you mean with 'orthogonal' that a cpu can be halted in either power level? I think this depends on the power level. If you consider ACPI C-states for example, there is only one C-state that has the processor execute instructions. The other states disable things like clock, bus clock, cache lines, ... In any state except the active C-state (C0) I think it has little sense to NOT halt the clock. So in these idle loops the cpu seems to go through a periodic disable/enable interrupts loop. a) when executing these instructions, surely the clock has to be running? b) why is this loop necessary? Isn't it possible to leave the wakeup interrupt enabled, which can then wakeup the cpu? c) if this is possible, then isn't it also possible to shut down the cpu (power it off), and let it wake up through an interrupt? Thanks , Thomas - Bart > > > -- > Bart Smaalders Solaris Kernel Performance > barts at cyber.eng.sun.com http://blogs.sun.com/barts > -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://mail.opensolaris.org/pipermail/laptop-discuss/attachments/20070510/2e805f4b/attachment.html>
