Hi Maciej, Maciej Browarski wrote: > Hello, > I'm interesting about privileges on Sparc T1/T2 processors. Is this same > as Rings on INTEL_x86s processors ? > How many levels are there ?
"An UltraSPARC Architecture virtual processor can run in nonprivileged mode, privileged mode, or hyperprivileged mode. In hyperprivileged mode, the processor can execute any instruction, including privileged instructions. In privileged mode, the processor can execute nonprivileged and privileged instructions. In nonprivileged mode, the processor can only execute nonprivileged instructions. In nonprivileged or privileged mode, an attempt to execute an instruction requiring greater privilege than the current mode causes a trap to hyperprivileged software." From UltraSPARC Architecture 2007 Specification, Hyperprivileged Edition http://opensparc-t2.sunsource.net/specs/UA2007-current-draft-HP-EXT.pdf > Is there any table (can be www page :) ) describing assembler > instruction and level on which this instruction can be execute ? > Sec 6.3 in the doc above will hopefully cover what you are looking for. > How look it in relation to hypervisor instruction ? HTH -- Liam
