My 2c on USB, lm-sensors and the NCT chip on this board.
> This is an RFC to port the PC Engines APU2 board to LEDE. Currently this
is based on my unofficial repo at https://github.com/riptidewave93/LEDE-APU2
and after a discussion on the lede-dev IRC on the best plan of action, which
was to move this device to a profile under x86_64.
> Default Packages:
> - flashrom - BIOS Upgrades
> - lm-sensors - Temp Monitoring
lm-sensors does not report individual core temps. FreeBSD/PFsense reports
all 4 core temps correctly.
Adapter: PCI adapter
temp1: +62.0°C (high = +70.0°C)
(crit = +105.0°C, hyst = +104.0°C)
root@lede:/# sensors -u
Adapter: PCI adapter
Could this be an issue of missing PCI device IDs? From
k10temp.c has these missing:
#define PCI_DEVICE_ID_AMD_16H_NB_F3 0x1533
#define PCI_DEVICE_ID_AMD_16H_NB_F4 0x1534
#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F3 0x1583
#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F4 0x1584
temp1max is set to 70C, the AMD GX-412TC in the APU uses the PCengines case
as a heatsink via thermal pads. If ambient temps are high (=>30C), I've seen
the CPU go as high as 73C, AMD rates the GX-412TC from 0C - 90C so should
temp1max be set to something like 75C?
The board has 2x USB3.0 ports at the rear and 2x USB 2 header on the SoC.
Could we also build 'lsusb' along with lspci? I'd recommend bundling the
usb-serial-kmod too as a lot of mini-pci devices present themselves as USB.
USB 3.0 seems to be working:
root@lede:/# lspci | grep XHCI
00:10.0 USB controller: Advanced Micro Devices, Inc. [AMD] FCH USB XHCI
Controller (rev 11)
/* According to the USB 3.0 spec, all USB 3.0 devices must support LPM.
However, there are some that don't, and they set the U1/U2 exit latencies to
With some quirks?
root@lede:/# dmesg|grep LPM
[ 1.324138] usb usb3: We don't know the algorithms for LPM for this host,
> - NCT5104D GPIO Driver
This is simply good to know info.
The NCT5104D I/O controller with an alternate BIOS (work in progress,
provided by PCengines support on request) can provide 2 more serial ports
(com3/4) while disabling GPIO/I2C. This is useful in some situations as COM1
is generally tied to serial console and sadly com2/UART b provided via
headers on the board does not provide all the signals. "UART-b is brought to
J3 unshifted. Even though J3 has five pins only transmit, receive and
ground are connected. - Paul"
Likely unrelated, perhaps at some point changes from CeroWRT could be
incorporated as the APU2 does suffer from buffer bloat -
Lede-dev mailing list