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--- Begin Message ---
Hello,
On Saturday, December 24, 2016 6:22:13 PM CET John Crispin wrote:
> On 24/12/2016 17:49, Martin Blumenstingl wrote:
> > On Sat, Dec 24, 2016 at 5:17 PM, antonio rossi <brac...@hotmail.com> wrote:
> >> Hi everybody,
> >>
> >> i'll try to make this as short as possible despite the large amount of
> >> information needed to describe the issue:
> >>
> >> i am working on adding support to LEDE/OpenWRT for DIR-815 A1, it's a
> >> RT3662+RT3092 device with an infamous IP175D switch IC.
> >> i managed to get everything working properly, save for the fact that
> >> network (both ethernet&wifi) works only after the stock bootloader
> >> does some funky stuff to set up the internal cpu port and/or switch
> >> to receive images via TFTP.
> > if only ethernet was affected then this might have been some pinctrl issue.
> > but since wifi is also affected this might be more of a clock (gate?) issue.
> >
> > maybe John has more information (or even a suspect) here?
>
>
>
>
> this sound like either
>
> 1) the cpu port is not configrued properly,
> 2) the switch is not configured properly
> 3) pinmux is failing
>
> the odd thing is that wifi fails without bootloader init. how does wifi
> fail exactly ?
I helped Antonio a bit. It turns out that the GE1 needs to be set to MII
mode (The default is RGMII). As far as I can tell, he had added this setting
already in the DTS. But the rt2880_port_init() didn't do anything with the
phy mode. I've made a patch (attached) that will set the bits in SYSCTL1
and he's currently testing it.
For now, I just added it to rt2880_port_init. However I don't know if the
RT2880 uses the same registers and bits (Don't have the RT2880 datasheet).
So, what do you think?
Regards,
Christian
--- a/drivers/net/ethernet/mediatek/mdio_rt2880.c 2016-12-25 13:26:58.456509613 +0100
+++ b/drivers/net/ethernet/mediatek/mdio_rt2880.c 2016-12-25 13:42:08.238633833 +0100
@@ -156,7 +156,7 @@ void rt2880_port_init(struct fe_priv *pr
const __be32 *id = of_get_property(np, "reg", NULL);
const __be32 *link;
int size;
- int phy_mode;
+ int phy_mode, set_phy_mode = -1;
if (!id || (be32_to_cpu(*id) != 0)) {
pr_err("%s: invalid port id\n", np->name);
@@ -175,10 +175,13 @@ void rt2880_port_init(struct fe_priv *pr
phy_mode = of_get_phy_mode(np);
switch (phy_mode) {
case PHY_INTERFACE_MODE_RGMII:
+ set_phy_mode = 0;
break;
case PHY_INTERFACE_MODE_MII:
+ set_phy_mode = 1;
break;
case PHY_INTERFACE_MODE_RMII:
+ set_phy_mode = 2;
break;
default:
if (!priv->phy->phy_fixed[0])
@@ -187,6 +190,18 @@ void rt2880_port_init(struct fe_priv *pr
break;
}
+ if (set_phy_mode != -1) {
+ u32 tmp;
+ u32 ge_offset;
+
+ ge_offset = 12 + id * 2; /* GE1 is at 12-13. GE2 is at 14-15 */
+
+ tmp = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1);
+ tmp = (t & ~GENMASK(ge_offset + 1, ge_offset)) |
+ (set_phy_mode << ge_offset);
+ rt_sysc_w32(tmp, RT3883_SYSC_REG_SYSCFG1);
+ }
+
priv->phy->phy_node[0] = of_parse_phandle(np, "phy-handle", 0);
if (!priv->phy->phy_node[0] && !priv->phy->phy_fixed[0])
return;
--- End Message ---
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