Date: Thu, 30 Oct 2003 01:50:36 -0800 From: PhotoEngineering <[EMAIL PROTECTED]> Subject: Re: [LIB] Amount of memory addressable??
At 12:42 AM 10/30/2003, you wrote:
Date: Thu, 30 Oct 2003 08:36:35 +0000 From: "Cerulean Skies" <[EMAIL PROTECTED]> Subject: Re: [LIB] Amount of memory addressable??
From: PhotoEngineering <[EMAIL PROTECTED]> Date: Wed, 29 Oct 2003 23:22:35 -0700
At 06:10 PM 10/28/2003, you wrote:Date: Tue, 28 Oct 2003 21:45:36 -0500 From: "Lewin A.R.W. Edwards" <[EMAIL PROTECTED]> Subject: Re: [LIB] Amount of memory addressable??
No you're not. The L1xx does not have an SDRAM controller, it has a DRAM controller compatible with EDO-mode DRAMs. Also, in order to change anything at all you'll have to hack an existing L1xx module, because it is proprietary in shape. There is no SDRAM pin-compatible with EDO, mainly because there would be no point; the two memory types are accessed quite differently.
Heh--it has a programmable GA setup as a edo dram controller. It is never a problem to access a differant type of ram as long as the new ram works fast enough and we already know sdram ram does. It fact it is almost exactly the same as edo in that when a flipflop is latched it stays latched as long as power is applied to the chip!!:-) Why would I need to hack a Libretto module? The pinout of the expansion connector is same as a 144 edo sodimm. No hacking needed. I thought of a sodimm first but EDO is so expensive even used that it seems worthless to stick with it.
I had addressed this issue a while ago, I believe. http://www.technoir.nu/libretto/list/2003/msg01323.html
I recently had to choose between a DRAM or a SDRAM controller for a microchip I'm designing, so I've had to pour over datasheets for both types of RAM. The interface to an EDO ram and a SDRAM is completely different. Grab a few datasheets and take a look, a DRAM controller cannot communicate with SDRAM at all.
Sure it can. The main differance is the length of time data is availible and since sdram is capabile of such increased speeds that can easily be overcome.
Secondly, the DRAM controller is part of the System Controller Gate Array. Are you certain it's a FPGA? I didn't get the part number of the chip the last time my Lib was disassembled.
Yes. Both the system controller and pcmcia controller are GAs.
If the gate array is not programmable and was designed only for 32 additional MBs, then we're done. There's nothing we can do to increase the memeory. It may be designed for 32 or 64 or more additional MBs, but the only way to find out is to interface it and see if it can detect the larger RAM sizes, unless someone figures out
It can see larger ram sizes. It is set up for 16k pages.
how to access any config registers in the gate array that selects the RAM size. If it's not designed for the larger RAM sizes but the gate array is programmable, now we're faced with reverse engineering a gate array, and that seems highly unpleasant.
Basically, for the amount of time I'd sink into this project, I might as well upgrade to a more powerful laptop.
There is no more powerful laptop than the Libretto 110CT especially with a gig or more of ram:-)!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
John [EMAIL PROTECTED]
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