You sir are a genius.

Changing the descriptors to report 512 bytes fixes the problem.

I'm aware of the limitations of EP1, but happy with it nevertheless. I
basically have a pair of very fast data channels (EP2OUT & EP6IN) for
exchanging data with an FPGA, and a pair of much slower channels (EP1OUT
& EP1IN) for JTAG.

The EP2&6 pair seems to require quad-buffering in order to get the best
throughput (I measure 43MiB/s when quad-buffered and about 33MiB/s when
double-buffered), which uses up all the 2KiB FIFO buffer space, leaving
only the 64 bytes for each of EP1OUT, EP1IN & EP0.

Since the JTAG streams are limited by the speed of the 8051, keeping the
send/receive chunks down to 64 bytes is perfectly fine, and possible
because I control the code on both sides.

The crucial piece of the puzzle which I was missing was the fact that
even though the "application" code on both ends of the link agrees to
use packets of 64 bytes or fewer, the "system" code in between needs to
see the EP1IN size reported as 512 bytes.

Thanks again!

Chris


On Thu, 2012-09-06 at 09:55 -0700, Tim Roberts wrote:
> Chris McClelland wrote:
> > Basically, the supplied FX2 firmware (in libusbx/fx2/fw/firmware.hex)
> > enumerates with two IN endpoints, EP1IN and EP2IN.
> 
> Endpoint 1 is the poor stepchild in the FX2.  The functionality is
> limited, the buffering is fixed and limited, and it uses different
> registers from the other endpoints.  As a general rule, you'll be much
> happier if you forget about it, and always restrict yourself to the
> even-numbered endpoints.
> 
> Your descriptors have the max packet size set to 64 for endpoint 1. 
> That's not valid.  In a high-speed devices, bulk endpoints must ALWAYS
> have a max packet size of 512.  That's required by the spec.  Because
> the FX2 only has a 64-byte buffer for endpoint 1, that presents a
> philosophical problem, and the FX2 data sheet points this out.  You have
> to report it as 512 bytes, but make sure you never try to do a packet
> larger than 64.
> 



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