Hi,
2014-08-08 5:50 GMT+02:00 Zhong Li <zhong...@intel.com>:
> Following haihao's suggestion, make gen6 phantom slice funcion can be
> re-used by SNB+.
>
> Signed-off-by: Zhong Li <zhong...@intel.com>
> ---
> src/gen6_mfd.c | 81
> ++--------------------------------------------
> src/i965_decoder_utils.c | 74 ++++++++++++++++++++++++++++++++++++++++++
> src/i965_decoder_utils.h | 7 ++++
> 3 files changed, 83 insertions(+), 79 deletions(-)
>
> diff --git a/src/gen6_mfd.c b/src/gen6_mfd.c
> index b3a8ef4..ea13e4f 100755
> --- a/src/gen6_mfd.c
> +++ b/src/gen6_mfd.c
> @@ -596,56 +596,6 @@ gen6_mfd_avc_slice_state(VADriverContextP ctx,
> ADVANCE_BCS_BATCH(batch);
> }
>
> -static void
> -gen6_mfd_avc_phantom_slice_state(VADriverContextP ctx,
> - VAPictureParameterBufferH264 *pic_param,
> - VASliceParameterBufferH264
> *next_slice_param,
> - struct gen6_mfd_context *gen6_mfd_context)
> -{
> - struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
> - int width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
> - int height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /*
> frame height */
> - int slice_hor_pos, slice_ver_pos, slice_start_mb_num,
> next_slice_hor_pos, next_slice_ver_pos;
> - int mbaff_picture = (!pic_param->pic_fields.bits.field_pic_flag &&
> -
> pic_param->seq_fields.bits.mb_adaptive_frame_field_flag);
> -
> - if (next_slice_param) {
> - int first_mb_in_next_slice;
> -
> - slice_hor_pos = 0;
> - slice_ver_pos = 0;
> - slice_start_mb_num = 0;
> - first_mb_in_next_slice = next_slice_param->first_mb_in_slice <<
> mbaff_picture;
> - next_slice_hor_pos = first_mb_in_next_slice % width_in_mbs;
> - next_slice_ver_pos = first_mb_in_next_slice / width_in_mbs;
> - } else {
> - slice_hor_pos = 0;
> - slice_ver_pos = height_in_mbs;
> - slice_start_mb_num = width_in_mbs * height_in_mbs / (1 +
> !!pic_param->pic_fields.bits.field_pic_flag);
> - next_slice_hor_pos = 0;
> - next_slice_ver_pos = 0;
> - }
> -
> - BEGIN_BCS_BATCH(batch, 11); /* FIXME: is it 10??? */
> - OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2));
> - OUT_BCS_BATCH(batch, 0);
> - OUT_BCS_BATCH(batch, 0);
> - OUT_BCS_BATCH(batch, 0);
> - OUT_BCS_BATCH(batch,
> - slice_ver_pos << 24 |
> - slice_hor_pos << 16 |
> - slice_start_mb_num << 0);
> - OUT_BCS_BATCH(batch,
> - next_slice_ver_pos << 16 |
> - next_slice_hor_pos << 0);
> - OUT_BCS_BATCH(batch, 0);
> - OUT_BCS_BATCH(batch, 0);
> - OUT_BCS_BATCH(batch, 0);
> - OUT_BCS_BATCH(batch, 0);
> - OUT_BCS_BATCH(batch, 0);
> - ADVANCE_BCS_BATCH(batch);
> -}
> -
> static inline void
> gen6_mfd_avc_ref_idx_state(VADriverContextP ctx,
> VAPictureParameterBufferH264 *pic_param,
> @@ -747,39 +697,12 @@ gen6_mfd_avc_bsd_object(VADriverContextP ctx,
> }
>
> static void
> -gen6_mfd_avc_phantom_slice_bsd_object(VADriverContextP ctx,
> - VAPictureParameterBufferH264
> *pic_param,
> - struct gen6_mfd_context
> *gen6_mfd_context)
> -{
> - struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
> -
> - BEGIN_BCS_BATCH(batch, 6);
> - OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2));
> - OUT_BCS_BATCH(batch, 0);
> - OUT_BCS_BATCH(batch, 0);
> - OUT_BCS_BATCH(batch, 0);
> - OUT_BCS_BATCH(batch, 0);
> - OUT_BCS_BATCH(batch, 0);
> - ADVANCE_BCS_BATCH(batch);
> -}
> -
> -static void
> -gen6_mfd_avc_phantom_slice(VADriverContextP ctx,
> - VAPictureParameterBufferH264 *pic_param,
> - VASliceParameterBufferH264 *next_slice_param,
> - struct gen6_mfd_context *gen6_mfd_context)
> -{
> - gen6_mfd_avc_phantom_slice_state(ctx, pic_param, next_slice_param,
> gen6_mfd_context);
> - gen6_mfd_avc_phantom_slice_bsd_object(ctx, pic_param, gen6_mfd_context);
> -}
> -
> -static void
> gen6_mfd_avc_phantom_slice_first(VADriverContextP ctx,
> VAPictureParameterBufferH264 *pic_param,
> VASliceParameterBufferH264
> *next_slice_param,
> struct gen6_mfd_context *gen6_mfd_context)
> {
> - gen6_mfd_avc_phantom_slice(ctx, pic_param, next_slice_param,
> gen6_mfd_context);
> + gen6_mfd_avc_phantom_slice(ctx, pic_param, next_slice_param,
> gen6_mfd_context->base.batch);
> }
>
> static void
> @@ -787,7 +710,7 @@ gen6_mfd_avc_phantom_slice_last(VADriverContextP ctx,
> VAPictureParameterBufferH264 *pic_param,
> struct gen6_mfd_context *gen6_mfd_context)
> {
> - gen6_mfd_avc_phantom_slice(ctx, pic_param, NULL, gen6_mfd_context);
> + gen6_mfd_avc_phantom_slice(ctx, pic_param, NULL,
> gen6_mfd_context->base.batch);
> }
>
> static void
> diff --git a/src/i965_decoder_utils.c b/src/i965_decoder_utils.c
> index 0af46cb..af5786a 100644
> --- a/src/i965_decoder_utils.c
> +++ b/src/i965_decoder_utils.c
> @@ -486,6 +486,80 @@ gen6_send_avc_ref_idx_state(
> frame_store
> );
> }
> +static void
Add a new line before this. :)
> +gen6_mfd_avc_phantom_slice_state(VADriverContextP ctx,
> + VAPictureParameterBufferH264 *pic_param,
> + VASliceParameterBufferH264
> *next_slice_param,
> + struct intel_batchbuffer *batch)
> +{
> + int width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
> + int height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /*
> frame height */
> + int slice_hor_pos, slice_ver_pos, slice_start_mb_num,
> next_slice_hor_pos, next_slice_ver_pos;
> + int mbaff_picture = (!pic_param->pic_fields.bits.field_pic_flag &&
> +
> pic_param->seq_fields.bits.mb_adaptive_frame_field_flag);
> +
> + if (next_slice_param) {
> + int first_mb_in_next_slice;
> +
> + slice_hor_pos = 0;
> + slice_ver_pos = 0;
> + slice_start_mb_num = 0;
> + first_mb_in_next_slice = next_slice_param->first_mb_in_slice <<
> mbaff_picture;
> + next_slice_hor_pos = first_mb_in_next_slice % width_in_mbs;
> + next_slice_ver_pos = first_mb_in_next_slice / width_in_mbs;
> + } else {
> + slice_hor_pos = 0;
> + slice_ver_pos = height_in_mbs;
> + slice_start_mb_num = width_in_mbs * height_in_mbs / (1 +
> !!pic_param->pic_fields.bits.field_pic_flag);
> + next_slice_hor_pos = 0;
> + next_slice_ver_pos = 0;
> + }
> +
> + BEGIN_BCS_BATCH(batch, 11); /* FIXME: is it 10??? */
Please fix the FIXME now, or remove this comment if this is OK.
+ check this is true for all generations now that it is a common
shared function.
> + OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2));
> + OUT_BCS_BATCH(batch, 0);
> + OUT_BCS_BATCH(batch, 0);
> + OUT_BCS_BATCH(batch, 0);
> + OUT_BCS_BATCH(batch,
> + slice_ver_pos << 24 |
> + slice_hor_pos << 16 |
> + slice_start_mb_num << 0);
> + OUT_BCS_BATCH(batch,
> + next_slice_ver_pos << 16 |
> + next_slice_hor_pos << 0);
> + OUT_BCS_BATCH(batch, 0);
> + OUT_BCS_BATCH(batch, 0);
> + OUT_BCS_BATCH(batch, 0);
> + OUT_BCS_BATCH(batch, 0);
> + OUT_BCS_BATCH(batch, 0);
> + ADVANCE_BCS_BATCH(batch);
> +}
> +
> +static void
> +gen6_mfd_avc_phantom_slice_bsd_object(VADriverContextP ctx,
> + VAPictureParameterBufferH264
> *pic_param,
> + struct intel_batchbuffer *batch)
> +{
> +
> + BEGIN_BCS_BATCH(batch, 6);
> + OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2));
> + OUT_BCS_BATCH(batch, 0);
> + OUT_BCS_BATCH(batch, 0);
> + OUT_BCS_BATCH(batch, 0);
> + OUT_BCS_BATCH(batch, 0);
> + OUT_BCS_BATCH(batch, 0);
> + ADVANCE_BCS_BATCH(batch);
> +}
> +
> +void
> +gen6_mfd_avc_phantom_slice(VADriverContextP ctx,
> + VAPictureParameterBufferH264 *pic_param,
> + VASliceParameterBufferH264 *next_slice_param,
> + struct intel_batchbuffer *batch)
> +{
> + gen6_mfd_avc_phantom_slice_state(ctx, pic_param, next_slice_param,
> batch);
> + gen6_mfd_avc_phantom_slice_bsd_object(ctx, pic_param, batch);
> +}
>
> /* Comparison function for sorting out the array of free frame store entries
> */
> static int
> diff --git a/src/i965_decoder_utils.h b/src/i965_decoder_utils.h
> index acd21f2..48ef814 100644
> --- a/src/i965_decoder_utils.h
> +++ b/src/i965_decoder_utils.h
> @@ -89,6 +89,13 @@ gen6_send_avc_ref_idx_state(
> const GenFrameStore frame_store[MAX_GEN_REFERENCE_FRAMES]
> );
>
> +void
> +gen6_mfd_avc_phantom_slice(VADriverContextP ctx,
> + VAPictureParameterBufferH264 *pic_param,
> + VASliceParameterBufferH264 *next_slice_param,
> + struct intel_batchbuffer *batch
> +);
> +
> VAStatus
> intel_decoder_sanity_check_input(VADriverContextP ctx,
> VAProfile profile,
The rest looks OK, assuming this is just factored code moved around. :)
Thanks,
--
Gwenole Beauchesne
Intel Corporation SAS / 2 rue de Paris, 92196 Meudon Cedex, France
Registration Number (RCS): Nanterre B 302 456 199
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