For each frame, the Intel HD Graphics hardware specification mandates that the following commands should be submitted, in-order: VEBOX_STATE, VEBOX_SURFACE_STATE(input), VEBOX_SURFACE_STATE(output), VEB_DI_IECP.
Signed-off-by: Gwenole Beauchesne <gwenole.beauche...@intel.com> --- src/gen75_vpp_vebox.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/src/gen75_vpp_vebox.c b/src/gen75_vpp_vebox.c index e06d8fe..9a60c27 100644 --- a/src/gen75_vpp_vebox.c +++ b/src/gen75_vpp_vebox.c @@ -1334,11 +1334,10 @@ VAStatus gen75_vebox_process_picture(VADriverContextP ctx, } else { intel_batchbuffer_start_atomic_veb(proc_ctx->batch, 0x1000); intel_batchbuffer_emit_mi_flush(proc_ctx->batch); - hsw_veb_surface_state(ctx, proc_ctx, INPUT_SURFACE); - hsw_veb_surface_state(ctx, proc_ctx, OUTPUT_SURFACE); hsw_veb_state_table_setup(ctx, proc_ctx); - hsw_veb_state_command(ctx, proc_ctx); + hsw_veb_surface_state(ctx, proc_ctx, INPUT_SURFACE); + hsw_veb_surface_state(ctx, proc_ctx, OUTPUT_SURFACE); hsw_veb_dndi_iecp_command(ctx, proc_ctx); intel_batchbuffer_end_atomic(proc_ctx->batch); intel_batchbuffer_flush(proc_ctx->batch); @@ -1632,11 +1631,10 @@ VAStatus gen8_vebox_process_picture(VADriverContextP ctx, } else { intel_batchbuffer_start_atomic_veb(proc_ctx->batch, 0x1000); intel_batchbuffer_emit_mi_flush(proc_ctx->batch); - hsw_veb_surface_state(ctx, proc_ctx, INPUT_SURFACE); - hsw_veb_surface_state(ctx, proc_ctx, OUTPUT_SURFACE); hsw_veb_state_table_setup(ctx, proc_ctx); - bdw_veb_state_command(ctx, proc_ctx); + hsw_veb_surface_state(ctx, proc_ctx, INPUT_SURFACE); + hsw_veb_surface_state(ctx, proc_ctx, OUTPUT_SURFACE); bdw_veb_dndi_iecp_command(ctx, proc_ctx); intel_batchbuffer_end_atomic(proc_ctx->batch); intel_batchbuffer_flush(proc_ctx->batch); -- 1.7.9.5 _______________________________________________ Libva mailing list Libva@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/libva