add context init function for AVC encoder
Signed-off-by: Pengfei Qu<pengfei...@intel.com>
Reviewed-by: Sean V Kelley<sea...@posteo.de>
---
src/i965_encoder_api.h | 47 ++++
src/i965_encoder_common.c | 124 +++++++++++
src/i965_encoder_common.h | 533 ++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 704 insertions(+)
create mode 100755 src/i965_encoder_api.h
create mode 100755 src/i965_encoder_common.c
create mode 100755 src/i965_encoder_common.h
diff --git a/src/i965_encoder_api.h b/src/i965_encoder_api.h
new file mode 100755
index 0000000..ebb0edc
--- /dev/null
+++ b/src/i965_encoder_api.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Pengfei Qu<pengfei...@intel.com>
+ *
+ */
+
+#ifndef _I965_ENCODER_API_H_
+#define _I965_ENCODER_API_H_
+
+#include<va/va.h>
+
+struct intel_encoder_context;
+struct hw_context;
+
+/* H264/AVC */
+extern Bool
+gen9_avc_vme_context_init(VADriverContextP ctx, struct intel_encoder_context
*encoder_context);
+
+extern Bool
+gen9_avc_pak_context_init(VADriverContextP ctx, struct intel_encoder_context
*encoder_context);
+
+extern VAStatus
+gen9_avc_coded_status(VADriverContextP ctx, char *buffer, struct hw_context
*hw_context);
+
+#endif // _I965_ENCODER_API_H_
diff --git a/src/i965_encoder_common.c b/src/i965_encoder_common.c
new file mode 100755
index 0000000..930aba9
--- /dev/null
+++ b/src/i965_encoder_common.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright ? 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWAR
+ *
+ * Authors:
+ * Pengfei Qu<pengfei...@intel.com>
+ *
+ */
+#include<stdio.h>
+#include<string.h>
+#include "intel_batchbuffer.h"
+#include "intel_driver.h"
+#include "i965_encoder_common.h"
+#include "i965_gpe_utils.h"
+
+
+const unsigned int table_enc_search_path[2][8][16] =
+{
+ // I-Frame& P-Frame
+ {
+ // MEMethod: 0
+ {
+ 0x120FF10F, 0x1E22E20D, 0x20E2FF10, 0x2EDD06FC, 0x11D33FF1,
0xEB1FF33D, 0x4EF1F1F1, 0xF1F21211,
+ 0x0DFFFFE0, 0x11201F1F, 0x1105F1CF, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000
+ },
+ // MEMethod: 1
+ {
+ 0x120FF10F, 0x1E22E20D, 0x20E2FF10, 0x2EDD06FC, 0x11D33FF1,
0xEB1FF33D, 0x4EF1F1F1, 0xF1F21211,
+ 0x0DFFFFE0, 0x11201F1F, 0x1105F1CF, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000
+ },
+ // MEMethod: 2
+ {
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000
+ },
+ // MEMethod: 3
+ {
+ 0x01010101, 0x11010101, 0x01010101, 0x11010101, 0x01010101,
0x11010101, 0x01010101, 0x11010101,
+ 0x01010101, 0x11010101, 0x01010101, 0x00010101, 0x00000000,
0x00000000, 0x00000000, 0x00000000
+ },
+ // MEMethod: 4
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010,
0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F,
0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 5
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010,
0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F,
0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 6
+ {
+ 0x120FF10F, 0x1E22E20D, 0x20E2FF10, 0x2EDD06FC, 0x11D33FF1,
0xEB1FF33D, 0x4EF1F1F1, 0xF1F21211,
+ 0x0DFFFFE0, 0x11201F1F, 0x1105F1CF, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000
+ },
+ // MEMethod: 7 used for mpeg2 encoding P frames
+ {
+ 0x1F11F10F, 0x2E22E2FE, 0x20E220DF, 0x2EDD06FC, 0x11D33FF1,
0xEB1FF33D, 0x02F1F1F1, 0x1F201111,
+ 0xF1EFFF0C, 0xF01104F1, 0x10FF0A50, 0x000FF1C0, 0x00000000,
0x00000000, 0x00000000, 0x00000000
+ }
+ },
+ // B-Frame
+ {
+ // MEMethod: 0
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010,
0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F,
0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 1
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010,
0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F,
0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 2
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010,
0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F,
0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 3
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010,
0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F,
0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 4
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010,
0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F,
0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 5
+ {
+ 0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010,
0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
+ 0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F,
0xF0F0F0F0, 0x00000000, 0x00000000
+ },
+ // MEMethod: 6
+ {
+ 0x120FF10F, 0x1E22E20D, 0x20E2FF10, 0x2EDD06FC, 0x11D33FF1,
0xEB1FF33D, 0x4EF1F1F1, 0xF1F21211,
+ 0x0DFFFFE0, 0x11201F1F, 0x1105F1CF, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000
+ },
+ // MEMethod: 7 used for mpeg2 encoding B frames
+ {
+ 0x1F11F10F, 0x2E22E2FE, 0x20E220DF, 0x2EDD06FC, 0x11D33FF1,
0xEB1FF33D, 0x02F1F1F1, 0x1F201111,
+ 0xF1EFFF0C, 0xF01104F1, 0x10FF0A50, 0x000FF1C0, 0x00000000,
0x00000000, 0x00000000, 0x00000000
+ }
+ }
+};
\ No newline at end of file
diff --git a/src/i965_encoder_common.h b/src/i965_encoder_common.h
new file mode 100755
index 0000000..bffbd8f
--- /dev/null
+++ b/src/i965_encoder_common.h
@@ -0,0 +1,533 @@
+/*
+ * Copyright ? 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWAR
+ *
+ * Authors:
+ * Pengfei Qu<pengfei...@intel.com>
+ *
+ */
+
+#ifndef _I965_COMMON_ENCODER_H
+#define _I965_COMMON_ENCODER_H
+
+#include<drm.h>
+#include<i915_drm.h>
+#include<intel_bufmgr.h>
+
+#include<va/va.h>
+#include "i965_encoder.h"
+#include "i965_gpe_utils.h"
+//#include "gen9_avc_encoder.h"
+
+struct encode_state;
+struct intel_encoder_context;
+
+/*
+ this file define the common structure for encoder, such as H264/H265/VP8/VP9
+*/
+
+#define INTEL_BRC_NONE 0
+#define INTEL_BRC_CBR 1
+#define INTEL_BRC_VBR 2
+#define INTEL_BRC_CQP 3
+#define INTEL_BRC_AVBR 4
+
+#define INTEL_BRC_INIT_FLAG_CBR 0x0010,
+#define INTEL_BRC_INIT_FLAG_VBR 0x0020,
+#define INTEL_BRC_INIT_FLAG_AVBR 0x0040,
+#define INTEL_BRC_INIT_FLAG_CQL 0x0080,
+#define INTEL_BRC_INIT_FLAG_FIELD_PIC 0x0100,
+#define INTEL_BRC_INIT_FLAG_ICQ 0x0200,
+#define INTEL_BRC_INIT_FLAG_VCM 0x0400,
+#define INTEL_BRC_INIT_FLAG_IGNORE_PICTURE_HEADER_SIZE 0x2000,
+#define INTEL_BRC_INIT_FLAG_QVBR 0x4000,
+#define INTEL_BRC_INIT_FLAG_DISABLE_MBBRC 0x8000
+
+
+#define INTEL_BRC_UPDATE_FLAG_FIELD 0x01,
+#define INTEL_BRC_UPDATE_FLAG_MBAFF (0x01<< 1),
+#define INTEL_BRC_UPDATE_FLAG_BOTTOM_FIELD (0x01<< 2),
+#define INTEL_BRC_UPDATE_FLAG_ACTUALQP (0x01<< 6),
+#define INTEL_BRC_UPDATE_FLAG_REFERENCE (0x01<< 7)
+
+#define INTEL_VME_MIN_ALLOWED_WIDTH_HEIGHT 48
+
+extern const unsigned int table_enc_search_path[2][8][16];
+
+// BRC Flag in BRC Init Kernel
+typedef enum _INTEL_ENCODE_BRCINIT_FLAG
+{
+ INTEL_ENCODE_BRCINIT_ISCBR = 0x0010,
+ INTEL_ENCODE_BRCINIT_ISVBR = 0x0020,
+ INTEL_ENCODE_BRCINIT_ISAVBR = 0x0040,
+ INTEL_ENCODE_BRCINIT_ISCQL = 0x0080,
+ INTEL_ENCODE_BRCINIT_FIELD_PIC = 0x0100,
+ INTEL_ENCODE_BRCINIT_ISICQ = 0x0200,
+ INTEL_ENCODE_BRCINIT_ISVCM = 0x0400,
+ INTEL_ENCODE_BRCINIT_IGNORE_PICTURE_HEADER_SIZE = 0x2000,
+ INTEL_ENCODE_BRCINIT_ISQVBR = 0x4000,
+ INTEL_ENCODE_BRCINIT_DISABLE_MBBRC = 0x8000
+} INTEL_ENCODE_BRCINIT_FLAG;
+
+// BRC Flag in BRC Update Kernel
+typedef enum _INTEL_ENCODE_BRCUPDATE_FLAG
+{
+ INTEL_ENCODE_BRCUPDATE_IS_FIELD = 0x01,
+ INTEL_ENCODE_BRCUPDATE_IS_MBAFF = (0x01<< 1),
+ INTEL_ENCODE_BRCUPDATE_IS_BOTTOM_FIELD = (0x01<< 2),
+ INTEL_ENCODE_BRCUPDATE_IS_ACTUALQP = (0x01<< 6),
+ INTEL_ENCODE_BRCUPDATE_IS_REFERENCE = (0x01<< 7)
+} INTEL_ENCODE_BRCUPDATE_FLAG;
+
+/*
+kernel operation related defines
+*/
+typedef enum _INTEL_GENERIC_ENC_OPERATION
+{
+ INTEL_GENERIC_ENC_SCALING4X = 0,
+ INTEL_GENERIC_ENC_SCALING2X,
+ INTEL_GENERIC_ENC_ME,
+ INTEL_GENERIC_ENC_BRC,
+ INTEL_GENERIC_ENC_MBENC,
+ INTEL_GENERIC_ENC_MBENC_WIDI,
+ INTEL_GENERIC_ENC_RESETVLINESTRIDE,
+ INTEL_GENERIC_ENC_MC,
+ INTEL_GENERIC_ENC_MBPAK,
+ INTEL_GENERIC_ENC_DEBLOCK,
+ INTEL_GENERIC_ENC_PREPROC,
+ INTEL_GENERIC_VDENC_ME,
+ INTEL_GENERIC_ENC_WP,
+ INTEL_GENERIC_ENC_SFD, // Static frame detection
+ INTEL_GENERIC_ENC_DYS
+} INTEL_GENERIC_ENC_OPERATION;
+
+typedef enum _INTEL_MEDIA_STATE_TYPE
+{
+ INTEL_MEDIA_STATE_OLP = 0,
+ INTEL_MEDIA_STATE_ENC_NORMAL = 1,
+ INTEL_MEDIA_STATE_ENC_PERFORMANCE = 2,
+ INTEL_MEDIA_STATE_ENC_QUALITY = 3,
+ INTEL_MEDIA_STATE_ENC_I_FRAME_DIST = 4,
+ INTEL_MEDIA_STATE_32X_SCALING = 5,
+ INTEL_MEDIA_STATE_16X_SCALING = 6,
+ INTEL_MEDIA_STATE_4X_SCALING = 7,
+ INTEL_MEDIA_STATE_32X_ME = 8,
+ INTEL_MEDIA_STATE_16X_ME = 9,
+ INTEL_MEDIA_STATE_4X_ME = 10,
+ INTEL_MEDIA_STATE_BRC_INIT_RESET = 11,
+ INTEL_MEDIA_STATE_BRC_UPDATE = 12,
+ INTEL_MEDIA_STATE_BRC_BLOCK_COPY = 13,
+ INTEL_MEDIA_STATE_HYBRID_PAK_P1 = 14,
+ INTEL_MEDIA_STATE_HYBRID_PAK_P2 = 15,
+ INTEL_MEDIA_STATE_ENC_I_FRAME_CHROMA = 16,
+ INTEL_MEDIA_STATE_ENC_I_FRAME_LUMA = 17,
+ INTEL_MEDIA_STATE_MPU_FHB = 18,
+ INTEL_MEDIA_STATE_TPU_FHB = 19,
+ INTEL_MEDIA_STATE_PA_COPY = 20,
+ INTEL_MEDIA_STATE_PL2_COPY = 21,
+ INTEL_MEDIA_STATE_ENC_WIDI = 22,
+ INTEL_MEDIA_STATE_2X_SCALING = 23,
+ INTEL_MEDIA_STATE_32x32_PU_MODE_DECISION = 24,
+ INTEL_MEDIA_STATE_16x16_PU_SAD = 25,
+ INTEL_MEDIA_STATE_16x16_PU_MODE_DECISION = 26,
+ INTEL_MEDIA_STATE_8x8_PU = 27,
+ INTEL_MEDIA_STATE_8x8_PU_FMODE = 28,
+ INTEL_MEDIA_STATE_32x32_B_INTRA_CHECK = 29,
+ INTEL_MEDIA_STATE_HEVC_B_MBENC = 30,
+ INTEL_MEDIA_STATE_RESET_VLINE_STRIDE = 31,
+ INTEL_MEDIA_STATE_HEVC_B_PAK = 32,
+ INTEL_MEDIA_STATE_HEVC_BRC_LCU_UPDATE = 33,
+ INTEL_MEDIA_STATE_ME_VDENC_STREAMIN = 34,
+ INTEL_MEDIA_STATE_VP9_ENC_I_32x32 = 35,
+ INTEL_MEDIA_STATE_VP9_ENC_I_16x16 = 36,
+ INTEL_MEDIA_STATE_VP9_ENC_P = 37,
+ INTEL_MEDIA_STATE_VP9_ENC_TX = 38,
+ INTEL_MEDIA_STATE_VP9_DYS = 39,
+ INTEL_MEDIA_STATE_VP9_PAK_LUMA_RECON = 40,
+ INTEL_MEDIA_STATE_VP9_PAK_CHROMA_RECON = 41,
+ INTEL_MEDIA_STATE_VP9_PAK_DEBLOCK_MASK = 42,
+ INTEL_MEDIA_STATE_VP9_PAK_LUMA_DEBLOCK = 43,
+ INTEL_MEDIA_STATE_VP9_PAK_CHROMA_DEBLOCK = 44,
+ INTEL_MEDIA_STATE_VP9_PAK_MC_PRED = 45,
+ INTEL_MEDIA_STATE_VP9_PAK_P_FRAME_LUMA_RECON = 46,
+ INTEL_MEDIA_STATE_VP9_PAK_P_FRAME_LUMA_RECON_32x32 = 47,
+ INTEL_MEDIA_STATE_VP9_PAK_P_FRAME_CHROMA_RECON = 48,
+ INTEL_MEDIA_STATE_VP9_PAK_P_FRAME_INTRA_LUMA_RECON = 49,
+ INTEL_MEDIA_STATE_VP9_PAK_P_FRAME_INTRA_CHROMA_RECON = 50,
+ INTEL_MEDIA_STATE_PREPROC = 51,
+ INTEL_MEDIA_STATE_ENC_WP = 52,
+ INTEL_MEDIA_STATE_HEVC_I_MBENC = 53,
+ INTEL_MEDIA_STATE_CSC_DS_COPY = 54,
+ INTEL_MEDIA_STATE_2X_4X_SCALING = 55,
+ INTEL_MEDIA_STATE_HEVC_LCU64_B_MBENC = 56,
+ INTEL_MEDIA_STATE_MB_BRC_UPDATE = 57,
+ INTEL_MEDIA_STATE_STATIC_FRAME_DETECTION = 58,
+ INTEL_MEDIA_STATE_HEVC_ROI = 59,
+ INTEL_MEDIA_STATE_SW_SCOREBOARD_INIT = 60,
+ INTEL_NUM_MEDIA_STATES = 61
+} INTEL_MEDIA_STATE_TYPE;
+
+struct encoder_kernel_parameter
+{
+ unsigned int curbe_size;
+ unsigned int inline_data_size;
+ unsigned int sampler_size;
+};
+
+struct encoder_scoreboard_parameter
+{
+ unsigned int mask;
+ unsigned int type;
+ unsigned int enable;
+ unsigned int walkpat_flag;
+};
+
+
+/*
+ME related defines
+*/
+#define INTEL_ENC_HME_4x 0
+#define INTEL_ENC_HME_16x 1
+#define INTEL_ENC_HME_32x 2
+
+/*
+ the definition for rate control
+*/
+#define GENERIC_BRC_SEQ 0x01
+#define GENERIC_BRC_HRD 0x02
+#define GENERIC_BRC_RC 0x04
+#define GENERIC_BRC_FR 0x08
+#define GENERIC_BRC_FAILURE (1<< 31)
+
+enum INTEL_ENC_KERNAL_MODE
+{
+ INTEL_ENC_KERNEL_QUALITY = 0,
+ INTEL_ENC_KERNEL_NORMAL,
+ INTEL_ENC_KERNEL_PERFORMANCE
+};
+
+enum INTEL_ENC_PRESET_MODE
+{
+ INTEL_PRESET_UNKNOWN = 0,
+ INTEL_PRESET_BEST_QUALITY = 1,
+ INTEL_PRESET_HI_QUALITY = 2,
+ INTEL_PRESET_OPT_QUALITY = 3,
+ INTEL_PRESET_OK_QUALITY = 5,
+ INTEL_PRESET_NO_SPEED = 1,
+ INTEL_PRESET_OPT_SPEED = 3,
+ INTEL_PRESET_RT_SPEED = 4,
+ INTEL_PRESET_HI_SPEED = 6,
+ INTEL_PRESET_BEST_SPEED = 7,
+ INTEL_PRESET_LOW_LATENCY = 0x10,
+ INTEL_PRESET_MULTIPASS = 0x20
+};