On Tue, 2017-01-17 at 08:40 +0800, Zhao Yakui wrote: > The access domain is not configured correctly for PAK_OBJ command > buffer. > And it causes that the buffer content is not synchronized correctly. > > At the same time the 64-byte is aligned for the boundary between > CPU and GPU access instead of 16-byte. > > Signed-off-by: Zhao Yakui <yakui.z...@intel.com>
Reviewed and tested all five patches in this series on core Linux and Chrome. lgtm, applied. Thanks, Sean > --- > src/gen8_mfc.c | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/src/gen8_mfc.c b/src/gen8_mfc.c > index 8e68c7c..7efe66e 100644 > --- a/src/gen8_mfc.c > +++ b/src/gen8_mfc.c > @@ -1562,7 +1562,7 @@ gen8_mfc_avc_batchbuffer_slice(VADriverContextP > ctx, > > intel_avc_slice_insert_packed_data(ctx, encode_state, > encoder_context, slice_index, slice_batch); > > - intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword > */ > + intel_batchbuffer_align(slice_batch, 64); /* aligned by an > Cache-line */ > head_offset = intel_batchbuffer_used_size(slice_batch); > > slice_batch->ptr += pSliceParameter->num_macroblocks * > AVC_PAK_LEN_IN_BYTE; > @@ -1576,7 +1576,7 @@ gen8_mfc_avc_batchbuffer_slice(VADriverContextP > ctx, > > > /* Aligned for tail */ > - intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword > */ > + intel_batchbuffer_align(slice_batch, 64); /* aligned by Cache- > line */ > if (last_slice) { > mfc_context->insert_object(ctx, > encoder_context, > @@ -1637,6 +1637,9 @@ > gen8_mfc_avc_batchbuffer_pipeline(VADriverContextP ctx, > OUT_BATCH(batch, CMD_MEDIA_STATE_FLUSH); > OUT_BATCH(batch, 0); > ADVANCE_BATCH(batch); > + > + intel_batchbuffer_free(slice_batch); > + mfc_context->aux_batchbuffer = NULL; > } > > intel_batchbuffer_end_atomic(batch);
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