VME pipeline:
add resource and surface allocation and free function
add init table for frame mbbrc update
add scaling kernel for AVC encoder
add BRC init reset kernel for AVC RC logic
add BRC frame update-kernel for AVC RC logic
add BRC MB level update kernel for AVC RC logic
add REF frame QA caculation and MB level const data
add MBENC kernel for AVC encoder
add ME kernel for AVC encoder
add WP/SFD kernel for AVC encoder
add kernel init/destroy function for AVC encoder
add kernel related parameter check function for AVC
add VME pipeline init prepare/run function for AVC encoder
Reviewed-by: Sean V Kelley<sea...@posteo.de>
Signed-off-by: Pengfei Qu<pengfei...@intel.com>
---
src/Makefile.am | 1 +
src/gen9_avc_encoder.c | 6027 ++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 6028 insertions(+)
create mode 100644 src/gen9_avc_encoder.c
diff --git a/src/Makefile.am b/src/Makefile.am
index c69e839..bf2f303 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -105,6 +105,7 @@ source_c = \
i965_encoder_common.c \
gen9_avc_const_def.c \
i965_avc_encoder_common.c \
+ gen9_avc_encoder.c \
$(NULL)
source_h = \
diff --git a/src/gen9_avc_encoder.c b/src/gen9_avc_encoder.c
new file mode 100644
index 0000000..d0ee3db
--- /dev/null
+++ b/src/gen9_avc_encoder.c
@@ -0,0 +1,6027 @@
+/*
+ * Copyright @ 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWAR OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Pengfei Qu<pengfei...@intel.com>
+ *
+ */
+
+#include<stdio.h>
+#include<stdlib.h>
+#include<stdbool.h>
+#include<string.h>
+#include<math.h>
+#include<assert.h>
+#include<va/va.h>
+
+#include "intel_batchbuffer.h"
+#include "intel_driver.h"
+
+#include "i965_defines.h"
+#include "i965_structs.h"
+#include "i965_drv_video.h"
+#include "i965_encoder.h"
+#include "i965_encoder_utils.h"
+#include "intel_media.h"
+
+#include "i965_gpe_utils.h"
+#include "i965_encoder_common.h"
+#include "i965_avc_encoder_common.h"
+#include "gen9_avc_encoder_kernels.h"
+#include "gen9_avc_encoder.h"
+#include "gen9_avc_const_def.h"
+
+#define MAX_URB_SIZE 4096 /* In register */
+#define NUM_KERNELS_PER_GPE_CONTEXT 1
+#define MBENC_KERNEL_BASE GEN9_AVC_KERNEL_MBENC_QUALITY_I
+
+#define OUT_BUFFER_2DW(batch, bo, is_target, delta) do { \
+ if (bo) { \
+ OUT_BCS_RELOC64(batch, \
+ bo, \
+ I915_GEM_DOMAIN_INSTRUCTION, \
+ is_target ? I915_GEM_DOMAIN_RENDER : 0, \
+ delta); \
+ } else { \
+ OUT_BCS_BATCH(batch, 0); \
+ OUT_BCS_BATCH(batch, 0); \
+ } \
+ } while (0)
+
+#define OUT_BUFFER_3DW(batch, bo, is_target, delta, attr) do { \
+ OUT_BUFFER_2DW(batch, bo, is_target, delta); \
+ OUT_BCS_BATCH(batch, attr); \
+ } while (0)
+
+
+static const uint32_t qm_flat[16] = {
+ 0x10101010, 0x10101010, 0x10101010, 0x10101010,
+ 0x10101010, 0x10101010, 0x10101010, 0x10101010,
+ 0x10101010, 0x10101010, 0x10101010, 0x10101010,
+ 0x10101010, 0x10101010, 0x10101010, 0x10101010
+};
+
+static const uint32_t fqm_flat[32] = {
+ 0x10001000, 0x10001000, 0x10001000, 0x10001000,
+ 0x10001000, 0x10001000, 0x10001000, 0x10001000,
+ 0x10001000, 0x10001000, 0x10001000, 0x10001000,
+ 0x10001000, 0x10001000, 0x10001000, 0x10001000,
+ 0x10001000, 0x10001000, 0x10001000, 0x10001000,
+ 0x10001000, 0x10001000, 0x10001000, 0x10001000,
+ 0x10001000, 0x10001000, 0x10001000, 0x10001000,
+ 0x10001000, 0x10001000, 0x10001000, 0x10001000
+};
+
+static unsigned int slice_type_kernel[3] = {1,2,0};
+
+const gen9_avc_brc_init_reset_curbe_data
gen9_avc_brc_init_reset_curbe_init_data =
+{
+ // unsigned int 0
+ {
+ 0
+ },
+
+ // unsigned int 1
+ {
+ 0
+ },
+
+ // unsigned int 2
+ {
+ 0
+ },
+
+ // unsigned int 3
+ {
+ 0
+ },
+
+ // unsigned int 4
+ {
+ 0
+ },
+
+ // unsigned int 5
+ {
+ 0
+ },
+
+ // unsigned int 6
+ {
+ 0
+ },
+
+ // unsigned int 7
+ {
+ 0
+ },
+
+ // unsigned int 8
+ {
+ 0,
+ 0
+ },
+
+ // unsigned int 9
+ {
+ 0,
+ 0
+ },
+
+ // unsigned int 10
+ {
+ 0,
+ 0
+ },
+
+ // unsigned int 11
+ {
+ 0,
+ 1
+ },
+
+ // unsigned int 12
+ {
+ 51,
+ 0
+ },
+
+ // unsigned int 13
+ {
+ 40,
+ 60,
+ 80,
+ 120
+ },
+
+ // unsigned int 14
+ {
+ 35,
+ 60,
+ 80,
+ 120
+ },
+
+ // unsigned int 15
+ {
+ 40,
+ 60,
+ 90,
+ 115
+ },
+
+ // unsigned int 16
+ {
+ 0,
+ 0,
+ 0,
+ 0
+ },
+
+ // unsigned int 17
+ {
+ 0,
+ 0,
+ 0,
+ 0
+ },
+
+ // unsigned int 18
+ {
+ 0,
+ 0,
+ 0,
+ 0
+ },
+
+ // unsigned int 19
+ {
+ 0,
+ 0,
+ 0,
+ 0
+ },
+
+ // unsigned int 20
+ {
+ 0,
+ 0,
+ 0,
+ 0
+ },
+
+ // unsigned int 21
+ {
+ 0,
+ 0,
+ 0,
+ 0
+ },
+
+ // unsigned int 22
+ {
+ 0,
+ 0,
+ 0,
+ 0
+ },
+
+ // unsigned int 23
+ {
+ 0
+ }
+};
+
+const gen9_avc_frame_brc_update_curbe_data
gen9_avc_frame_brc_update_curbe_init_data =
+{
+ // unsigned int 0
+ {
+ 0
+ },
+
+ // unsigned int 1
+ {
+ 0
+ },
+
+ // unsigned int 2
+ {
+ 0
+ },
+
+ // unsigned int 3
+ {
+ 10,
+ 50
+ },
+
+ // unsigned int 4
+ {
+ 100,
+ 150
+ },
+
+ // unsigned int 5
+ {
+ 0,
+ 0,
+ 0,
+ 0
+ },
+
+ // unsigned int 6
+ {
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0
+ },
+
+ // unsigned int 7
+ {
+ 0
+ },
+
+ // unsigned int 8
+ {
+ 1,
+ 1,
+ 3,
+ 2
+ },
+
+ // unsigned int 9
+ {
+ 1,
+ 40,
+ 5,
+ 5
+ },
+
+ // unsigned int 10
+ {
+ 3,
+ 1,
+ 7,
+ 18
+ },
+
+ // unsigned int 11
+ {
+ 25,
+ 37,
+ 40,
+ 75
+ },
+
+ // unsigned int 12
+ {
+ 97,
+ 103,
+ 125,
+ 160
+ },
+
+ // unsigned int 13
+ {
+ -3,
+ -2,
+ -1,
+ 0
+ },
+
+ // unsigned int 14
+ {
+ 1,
+ 2,
+ 3,
+ 0xff
+ },
+
+ // unsigned int 15
+ {
+ 0,
+ 0,
+ 0,
+ 0
+ },
+
+ // unsigned int 16
+ {
+ 0
+ },
+
+ // unsigned int 17
+ {
+ 0
+ },
+
+ // unsigned int 18
+ {
+ 0
+ },
+
+ // unsigned int 19
+ {
+ 0
+ },
+
+ // unsigned int 20
+ {
+ 0
+ },
+
+ // unsigned int 21
+ {
+ 0
+ },
+
+ // unsigned int 22
+ {
+ 0
+ },
+
+ // unsigned int 23
+ {
+ 0
+ },
+
+};
+
+static void
+gen9_avc_update_misc_parameters(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ struct encoder_vme_mfc_context * vme_context = (struct
encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct generic_enc_codec_state * generic_state = (struct
generic_enc_codec_state * )vme_context->generic_enc_state;
+ int i;
+
+ /* brc */
+ generic_state->max_bit_rate =
ALIGN(encoder_context->brc.bits_per_second[0], 1000) / 1000;
+ generic_state->window_size = encoder_context->brc.window_size;
+ generic_state->brc_need_reset = encoder_context->brc.need_reset;
+
+ if (generic_state->internal_rate_mode == VA_RC_CBR) {
+ generic_state->min_bit_rate = generic_state->max_bit_rate;
+ generic_state->mb_brc_enabled =
encoder_context->brc.mb_rate_control[0];
+
+ if (generic_state->target_bit_rate != generic_state->max_bit_rate) {
+ generic_state->target_bit_rate = generic_state->max_bit_rate;
+ generic_state->brc_need_reset = 1;
+ }
+ } else if (generic_state->internal_rate_mode == VA_RC_VBR) {
+ generic_state->min_bit_rate = generic_state->max_bit_rate * (2 *
encoder_context->brc.target_percentage[0] - 100) / 100;
+ generic_state->mb_brc_enabled =
encoder_context->brc.mb_rate_control[0];
+
+ if (generic_state->target_bit_rate != generic_state->max_bit_rate *
encoder_context->brc.target_percentage[0] / 100) {
+ generic_state->target_bit_rate = generic_state->max_bit_rate *
encoder_context->brc.target_percentage[0] / 100;
+ generic_state->brc_need_reset = 1;
+ }
+ }
+
+ /* frame rate */
+ if (generic_state->internal_rate_mode != VA_RC_CQP)
+ {
+ generic_state->frames_per_100s =
encoder_context->brc.framerate[0].num/encoder_context->brc.framerate[0].den * 100;
+ generic_state->frame_rate =
encoder_context->brc.framerate[0].num/encoder_context->brc.framerate[0].den ;
+ }
+ /* HRD */
+ if (generic_state->internal_rate_mode != VA_RC_CQP)
+ {
+ generic_state->vbv_buffer_size_in_bit =
encoder_context->brc.hrd_buffer_size;//misc->buffer_size;
+ generic_state->init_vbv_buffer_fullness_in_bit =
encoder_context->brc.hrd_initial_buffer_fullness;//misc->initial_buffer_fullness;
+ }
+
+ /* ROI */
+ generic_state->num_roi = MIN(encoder_context->brc.num_roi, 3);
+ if (generic_state->num_roi> 0) {
+ generic_state->max_delta_qp = encoder_context->brc.roi_max_delta_qp;
+ generic_state->min_delta_qp = encoder_context->brc.roi_min_delta_qp;
+
+ for (i = 0; i< generic_state->num_roi; i++) {
+ generic_state->roi[i].left = encoder_context->brc.roi[i].left;
+ generic_state->roi[i].right = encoder_context->brc.roi[i].right;
+ generic_state->roi[i].top = encoder_context->brc.roi[i].top;
+ generic_state->roi[i].bottom = encoder_context->brc.roi[i].bottom;
+ generic_state->roi[i].value = encoder_context->brc.roi[i].value;
+
+ generic_state->roi[i].left /= 16;
+ generic_state->roi[i].right /= 16;
+ generic_state->roi[i].top /= 16;
+ generic_state->roi[i].bottom /= 16;
+ }
+ }
+
+}
+
+static bool
+intel_avc_get_kernel_header_and_size(void
*pvbinary,
+ int
binary_size,
+ INTEL_GENERIC_ENC_OPERATION
operation,
+ int
krnstate_idx,
+ struct i965_kernel
*ret_kernel)
+{
+ typedef uint32_t BIN_PTR[4];
+
+ char *bin_start;
+ gen9_avc_encoder_kernel_header *pkh_table;
+ kernel_header *pcurr_header, *pinvalid_entry, *pnext_header;
+ int next_krnoffset;
+
+ if (!pvbinary || !ret_kernel)
+ return false;
+
+ bin_start = (char *)pvbinary;
+ pkh_table = (gen9_avc_encoder_kernel_header *)pvbinary;
+ pinvalid_entry =&(pkh_table->static_detection) + 1;
+ next_krnoffset = binary_size;
+
+ if (operation == INTEL_GENERIC_ENC_SCALING4X)
+ {
+ pcurr_header =&pkh_table->ply_dscale_ply;
+ }
+ else if (operation == INTEL_GENERIC_ENC_SCALING2X)
+ {
+ pcurr_header =&pkh_table->ply_2xdscale_ply;
+ }
+ else if (operation == INTEL_GENERIC_ENC_ME)
+ {
+ pcurr_header =&pkh_table->me_p;
+ }
+ else if (operation == INTEL_GENERIC_ENC_BRC)
+ {
+ pcurr_header =&pkh_table->frame_brc_init;
+ }
+ else if (operation == INTEL_GENERIC_ENC_MBENC)
+ {
+ pcurr_header =&pkh_table->mbenc_quality_I;
+ }
+ else if (operation == INTEL_GENERIC_ENC_WP)
+ {
+ pcurr_header =&pkh_table->wp;
+ }
+ else if (operation == INTEL_GENERIC_ENC_SFD)
+ {
+ pcurr_header =&pkh_table->static_detection;
+ }
+ else
+ {
+ return false;
+ }
+
+ pcurr_header += krnstate_idx;
+ ret_kernel->bin = (const BIN_PTR *)(bin_start +
(pcurr_header->kernel_start_pointer<< 6));
+
+ pnext_header = (pcurr_header + 1);
+ if (pnext_header< pinvalid_entry)
+ {
+ next_krnoffset = pnext_header->kernel_start_pointer<< 6;
+ }
+ ret_kernel->size = next_krnoffset - (pcurr_header->kernel_start_pointer<<
6);
+
+ return true;
+}
+static void
+gen9_free_surfaces_avc(void **data)
+{
+ struct gen9_surface_avc *avc_surface;
+
+ if (!data || !*data)
+ return;
+
+ avc_surface = *data;
+
+ if (avc_surface->scaled_4x_surface_obj) {
+
i965_DestroySurfaces(avc_surface->ctx,&avc_surface->scaled_4x_surface_id, 1);
+ avc_surface->scaled_4x_surface_id = VA_INVALID_SURFACE;
+ avc_surface->scaled_4x_surface_obj = NULL;
+ }
+
+ if (avc_surface->scaled_16x_surface_obj) {
+
i965_DestroySurfaces(avc_surface->ctx,&avc_surface->scaled_16x_surface_id, 1);
+ avc_surface->scaled_16x_surface_id = VA_INVALID_SURFACE;
+ avc_surface->scaled_16x_surface_obj = NULL;
+ }
+
+ if (avc_surface->scaled_32x_surface_obj) {
+
i965_DestroySurfaces(avc_surface->ctx,&avc_surface->scaled_32x_surface_id, 1);
+ avc_surface->scaled_32x_surface_id = VA_INVALID_SURFACE;
+ avc_surface->scaled_32x_surface_obj = NULL;
+ }
+
+ i965_free_gpe_resource(&avc_surface->res_mb_code_surface);
+ i965_free_gpe_resource(&avc_surface->res_mv_data_surface);
+ i965_free_gpe_resource(&avc_surface->res_ref_pic_select_surface);
+
+ dri_bo_unreference(avc_surface->dmv_top);
+ avc_surface->dmv_top = NULL;
+ dri_bo_unreference(avc_surface->dmv_bottom);
+ avc_surface->dmv_bottom = NULL;
+
+ free(avc_surface);
+
+ *data = NULL;
+
+ return;
+}
+
+static VAStatus
+gen9_avc_init_check_surfaces(VADriverContextP ctx,
+ struct object_surface *obj_surface,
+ struct intel_encoder_context *encoder_context,
+ struct avc_surface_param *surface_param)
+{
+ struct i965_driver_data *i965 = i965_driver_data(ctx);
+ struct encoder_vme_mfc_context * vme_context = (struct
encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct avc_enc_state * avc_state = (struct avc_enc_state *
)vme_context->private_enc_state;
+ struct generic_enc_codec_state * generic_state = (struct
generic_enc_codec_state * )vme_context->generic_enc_state;
+
+ struct gen9_surface_avc *avc_surface;
+ int downscaled_width_4x, downscaled_height_4x;
+ int downscaled_width_16x, downscaled_height_16x;
+ int downscaled_width_32x, downscaled_height_32x;
+ int size = 0;
+ unsigned int frame_width_in_mbs = ALIGN(surface_param->frame_width,16) /
16;
+ unsigned int frame_height_in_mbs = ALIGN(surface_param->frame_height,16) /
16;
+ unsigned int frame_mb_nums = frame_width_in_mbs * frame_height_in_mbs;
+ int allocate_flag = 1;
+ int width,height;
+
+ if (!obj_surface || !obj_surface->bo)
+ return VA_STATUS_ERROR_INVALID_SURFACE;
+
+ if (obj_surface->private_data&&
+ obj_surface->free_private_data != gen9_free_surfaces_avc) {
+ obj_surface->free_private_data(&obj_surface->private_data);
+ obj_surface->private_data = NULL;
+ }
+
+ if (obj_surface->private_data) {
+ return VA_STATUS_SUCCESS;
+ }
+
+ avc_surface = calloc(1, sizeof(struct gen9_surface_avc));
+
+ if (!avc_surface)
+ return VA_STATUS_ERROR_ALLOCATION_FAILED;
+
+ avc_surface->ctx = ctx;
+ obj_surface->private_data = avc_surface;
+ obj_surface->free_private_data = gen9_free_surfaces_avc;
+
+ downscaled_width_4x = generic_state->frame_width_4x;
+ downscaled_height_4x = generic_state->frame_height_4x;
+
+ i965_CreateSurfaces(ctx,
+ downscaled_width_4x,
+ downscaled_height_4x,
+ VA_RT_FORMAT_YUV420,
+ 1,
+&avc_surface->scaled_4x_surface_id);
+
+ avc_surface->scaled_4x_surface_obj =
SURFACE(avc_surface->scaled_4x_surface_id);
+
+ if (!avc_surface->scaled_4x_surface_obj) {
+ return VA_STATUS_ERROR_ALLOCATION_FAILED;
+ }
+
+ i965_check_alloc_surface_bo(ctx, avc_surface->scaled_4x_surface_obj, 1,
+ VA_FOURCC('N', 'V', '1', '2'),
SUBSAMPLE_YUV420);
+
+ downscaled_width_16x = generic_state->frame_width_16x;
+ downscaled_height_16x = generic_state->frame_height_16x;
+ i965_CreateSurfaces(ctx,
+ downscaled_width_16x,
+ downscaled_height_16x,
+ VA_RT_FORMAT_YUV420,
+ 1,
+&avc_surface->scaled_16x_surface_id);
+ avc_surface->scaled_16x_surface_obj =
SURFACE(avc_surface->scaled_16x_surface_id);
+
+ if (!avc_surface->scaled_16x_surface_obj) {
+ return VA_STATUS_ERROR_ALLOCATION_FAILED;
+ }
+
+ i965_check_alloc_surface_bo(ctx, avc_surface->scaled_16x_surface_obj, 1,
+ VA_FOURCC('N', 'V', '1', '2'),
SUBSAMPLE_YUV420);
+
+ downscaled_width_32x = generic_state->frame_width_32x;
+ downscaled_height_32x = generic_state->frame_height_32x;
+ i965_CreateSurfaces(ctx,
+ downscaled_width_32x,
+ downscaled_height_32x,
+ VA_RT_FORMAT_YUV420,
+ 1,
+&avc_surface->scaled_32x_surface_id);
+ avc_surface->scaled_32x_surface_obj =
SURFACE(avc_surface->scaled_32x_surface_id);
+
+ if (!avc_surface->scaled_32x_surface_obj) {
+ return VA_STATUS_ERROR_ALLOCATION_FAILED;
+ }
+
+ i965_check_alloc_surface_bo(ctx, avc_surface->scaled_32x_surface_obj, 1,
+ VA_FOURCC('N', 'V', '1', '2'),
SUBSAMPLE_YUV420);
+
+ /*mb code and mv data for each frame*/
+ size = frame_mb_nums * 16 * 4;
+ allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
+&avc_surface->res_mb_code_surface,
+ ALIGN(size,0x1000),
+ "mb code buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+
+ size = frame_mb_nums * 32 * 4;
+ allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
+&avc_surface->res_mv_data_surface,
+ ALIGN(size,0x1000),
+ "mv data buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+
+ /* ref pic list*/
+ if(avc_state->ref_pic_select_list_supported)
+ {
+ width = ALIGN(frame_width_in_mbs * 8,64);
+ height= frame_height_in_mbs ;
+ allocate_flag = i965_gpe_allocate_2d_resource(i965->intel.bufmgr,
+&avc_surface->res_ref_pic_select_surface,
+ width, height,
+ width,
+ "Ref pic select list buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+ }
+
+ /*direct mv*/
+ avc_surface->dmv_top =
+ dri_bo_alloc(i965->intel.bufmgr,
+ "direct mv top Buffer",
+ 68 * frame_mb_nums,
+ 64);
+ avc_surface->dmv_bottom =
+ dri_bo_alloc(i965->intel.bufmgr,
+ "direct mv bottom Buffer",
+ 68 * frame_mb_nums,
+ 64);
+ assert(avc_surface->dmv_top);
+ assert(avc_surface->dmv_bottom);
+
+ return VA_STATUS_SUCCESS;
+
+failed_allocation:
+ return VA_STATUS_ERROR_ALLOCATION_FAILED;
+}
+
+static VAStatus
+gen9_avc_allocate_resources(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ struct i965_driver_data *i965 = i965_driver_data(ctx);
+ struct encoder_vme_mfc_context * vme_context = (struct
encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context
* )vme_context->private_enc_ctx;
+ struct generic_enc_codec_state * generic_state = (struct
generic_enc_codec_state * )vme_context->generic_enc_state;
+ struct avc_enc_state * avc_state = (struct avc_enc_state *
)vme_context->private_enc_state;
+ unsigned int size = 0;
+ unsigned int width = 0;
+ unsigned int height = 0;
+ unsigned char * data = NULL;
+ int allocate_flag = 1;
+ int i = 0;
+
+ /*all the surface/buffer are allocated here*/
+
+ /*second level batch buffer for image state write when cqp etc*/
+ i965_free_gpe_resource(&avc_ctx->res_image_state_batch_buffer_2nd_level);
+ size = INTEL_AVC_IMAGE_STATE_CMD_SIZE ;
+ allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
+&avc_ctx->res_image_state_batch_buffer_2nd_level,
+ ALIGN(size,0x1000),
+ "second levle batch (image state write) buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+
+ /* scaling related surface */
+ if(avc_state->mb_status_supported)
+ {
+ i965_free_gpe_resource(&avc_ctx->res_mb_status_buffer);
+ size = (generic_state->frame_width_in_mbs *
generic_state->frame_height_in_mbs * 16 * 4 + 1023)&~0x3ff;
+ allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
+&avc_ctx->res_mb_status_buffer,
+ ALIGN(size,0x1000),
+ "MB statistics output buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+ i965_zero_gpe_resource(&avc_ctx->res_mb_status_buffer);
+ }
+
+ if(avc_state->flatness_check_supported)
+ {
+ width = generic_state->frame_width_in_mbs * 4;
+ height= generic_state->frame_height_in_mbs * 4;
+ i965_free_gpe_resource(&avc_ctx->res_flatness_check_surface);
+ allocate_flag = i965_gpe_allocate_2d_resource(i965->intel.bufmgr,
+&avc_ctx->res_flatness_check_surface,
+ width, height,
+ ALIGN(width,64),
+ "Flatness check buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+ }
+ /* me related surface */
+ width = generic_state->downscaled_width_4x_in_mb * 8;
+ height= generic_state->downscaled_height_4x_in_mb * 4 * 10;
+ i965_free_gpe_resource(&avc_ctx->s4x_memv_distortion_buffer);
+ allocate_flag = i965_gpe_allocate_2d_resource(i965->intel.bufmgr,
+&avc_ctx->s4x_memv_distortion_buffer,
+ width, height,
+ ALIGN(width,64),
+ "4x MEMV distortion buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+ i965_zero_gpe_resource(&avc_ctx->s4x_memv_distortion_buffer);
+
+ width = (generic_state->downscaled_width_4x_in_mb + 7)/8 * 64;
+ height= (generic_state->downscaled_height_4x_in_mb + 1)/2 * 8;
+ i965_free_gpe_resource(&avc_ctx->s4x_memv_min_distortion_brc_buffer);
+ allocate_flag = i965_gpe_allocate_2d_resource(i965->intel.bufmgr,
+&avc_ctx->s4x_memv_min_distortion_brc_buffer,
+ width, height,
+ width,
+ "4x MEMV min distortion brc buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+ i965_zero_gpe_resource(&avc_ctx->s4x_memv_min_distortion_brc_buffer);
+
+
+ width = ALIGN(generic_state->downscaled_width_4x_in_mb * 32,64);
+ height= generic_state->downscaled_height_4x_in_mb * 4 * 2 * 10;
+ i965_free_gpe_resource(&avc_ctx->s4x_memv_data_buffer);
+ allocate_flag = i965_gpe_allocate_2d_resource(i965->intel.bufmgr,
+&avc_ctx->s4x_memv_data_buffer,
+ width, height,
+ width,
+ "4x MEMV data buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+ i965_zero_gpe_resource(&avc_ctx->s4x_memv_data_buffer);
+
+
+ width = ALIGN(generic_state->downscaled_width_16x_in_mb * 32,64);
+ height= generic_state->downscaled_height_16x_in_mb * 4 * 2 * 10 ;
+ i965_free_gpe_resource(&avc_ctx->s16x_memv_data_buffer);
+ allocate_flag = i965_gpe_allocate_2d_resource(i965->intel.bufmgr,
+&avc_ctx->s16x_memv_data_buffer,
+ width, height,
+ width,
+ "16x MEMV data buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+ i965_zero_gpe_resource(&avc_ctx->s16x_memv_data_buffer);
+
+
+ width = ALIGN(generic_state->downscaled_width_32x_in_mb * 32,64);
+ height= generic_state->downscaled_height_32x_in_mb * 4 * 2 * 10 ;
+ i965_free_gpe_resource(&avc_ctx->s32x_memv_data_buffer);
+ allocate_flag = i965_gpe_allocate_2d_resource(i965->intel.bufmgr,
+&avc_ctx->s32x_memv_data_buffer,
+ width, height,
+ width,
+ "32x MEMV data buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+ i965_zero_gpe_resource(&avc_ctx->s32x_memv_data_buffer);
+
+
+ if(!generic_state->brc_allocated)
+ {
+ /*brc related surface */
+ i965_free_gpe_resource(&avc_ctx->res_brc_history_buffer);
+ size = 864;
+ allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
+&avc_ctx->res_brc_history_buffer,
+ ALIGN(size,0x1000),
+ "brc history buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+
+
i965_free_gpe_resource(&avc_ctx->res_brc_pre_pak_statistics_output_buffer);
+ size = 64;//44
+ allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
+&avc_ctx->res_brc_pre_pak_statistics_output_buffer,
+ ALIGN(size,0x1000),
+ "brc pak statistic buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+
+ i965_free_gpe_resource(&avc_ctx->res_brc_image_state_read_buffer);
+ size = INTEL_AVC_IMAGE_STATE_CMD_SIZE * 7;
+ allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
+&avc_ctx->res_brc_image_state_read_buffer,
+ ALIGN(size,0x1000),
+ "brc image state read buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+
+ i965_free_gpe_resource(&avc_ctx->res_brc_image_state_write_buffer);
+ size = INTEL_AVC_IMAGE_STATE_CMD_SIZE * 7;
+ allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
+&avc_ctx->res_brc_image_state_write_buffer,
+ ALIGN(size,0x1000),
+ "brc image state write buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+
+ width = ALIGN(64,64);
+ height= 44;
+ i965_free_gpe_resource(&avc_ctx->res_brc_const_data_buffer);
+ allocate_flag = i965_gpe_allocate_2d_resource(i965->intel.bufmgr,
+&avc_ctx->res_brc_const_data_buffer,
+ width, height,
+ width,
+ "brc const data buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+
+ if(generic_state->brc_distortion_buffer_supported)
+ {
+ width = ALIGN(generic_state->downscaled_width_4x_in_mb * 8,64);
+ height= ALIGN(generic_state->downscaled_height_4x_in_mb * 4,8);
+ width = (generic_state->downscaled_width_4x_in_mb + 7)/8 * 64;
+ height= (generic_state->downscaled_height_4x_in_mb + 1)/2 * 8;
+ i965_free_gpe_resource(&avc_ctx->res_brc_dist_data_surface);
+ allocate_flag = i965_gpe_allocate_2d_resource(i965->intel.bufmgr,
+&avc_ctx->res_brc_dist_data_surface,
+ width, height,
+ width,
+ "brc dist data buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+ i965_zero_gpe_resource(&avc_ctx->res_brc_dist_data_surface);
+ }
+
+ if(generic_state->brc_roi_enable)
+ {
+ width = ALIGN(generic_state->downscaled_width_4x_in_mb * 16,64);
+ height= ALIGN(generic_state->downscaled_height_4x_in_mb * 4,8);
+ i965_free_gpe_resource(&avc_ctx->res_mbbrc_roi_surface);
+ allocate_flag = i965_gpe_allocate_2d_resource(i965->intel.bufmgr,
+&avc_ctx->res_mbbrc_roi_surface,
+ width, height,
+ width,
+ "mbbrc roi buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+ i965_zero_gpe_resource(&avc_ctx->res_mbbrc_roi_surface);
+ }
+
+ /*mb qp in mb brc*/
+ width = ALIGN(generic_state->downscaled_width_4x_in_mb * 4,64);
+ height= ALIGN(generic_state->downscaled_height_4x_in_mb * 4,8);
+ i965_free_gpe_resource(&avc_ctx->res_mbbrc_mb_qp_data_surface);
+ allocate_flag = i965_gpe_allocate_2d_resource(i965->intel.bufmgr,
+&avc_ctx->res_mbbrc_mb_qp_data_surface,
+ width, height,
+ width,
+ "mbbrc mb qp buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+
+ i965_free_gpe_resource(&avc_ctx->res_mbbrc_const_data_buffer);
+ size = 16 * 52 * 4;
+ allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
+&avc_ctx->res_mbbrc_const_data_buffer,
+ ALIGN(size,0x1000),
+ "mbbrc const data buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+
+ generic_state->brc_allocated = 1;
+ }
+
+ /*mb qp external*/
+ if(avc_state->mb_qp_data_enable)
+ {
+ width = ALIGN(generic_state->downscaled_width_4x_in_mb * 4,64);
+ height= ALIGN(generic_state->downscaled_height_4x_in_mb * 4,8);
+ i965_free_gpe_resource(&avc_ctx->res_mb_qp_data_surface);
+ allocate_flag = i965_gpe_allocate_2d_resource(i965->intel.bufmgr,
+&avc_ctx->res_mb_qp_data_surface,
+ width, height,
+ width,
+ "external mb qp buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+ }
+
+
+ /* maybe it is not needed by now. it is used in crypt mode*/
+ i965_free_gpe_resource(&avc_ctx->res_brc_mbenc_curbe_write_buffer);
+ size = ALIGN(sizeof(gen9_avc_mbenc_curbe_data), 64) + ALIGN(sizeof(struct
gen8_interface_descriptor_data), 64) ;//* NUM_GEN9_AVC_KERNEL_MBENC;
+ allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
+&avc_ctx->res_brc_mbenc_curbe_write_buffer,
+ size,
+ "mbenc curbe data buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+
+ /* mbenc related surface. it share most of surface with other kernels
*/
+ if(avc_state->arbitrary_num_mbs_in_slice)
+ {
+ width = (generic_state->frame_width_in_mbs + 1) * 64;
+ height= generic_state->frame_height_in_mbs ;
+ i965_free_gpe_resource(&avc_ctx->res_mbenc_slice_map_surface);
+ allocate_flag = i965_gpe_allocate_2d_resource(i965->intel.bufmgr,
+&avc_ctx->res_mbenc_slice_map_surface,
+ width, height,
+ width,
+ "slice map buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+
+ /*generate slice map,default one slice per frame.*/
+ }
+
+ /* sfd related surface */
+ if(avc_state->sfd_enable)
+ {
+ i965_free_gpe_resource(&avc_ctx->res_sfd_output_buffer);
+ size = 128;
+ allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
+&avc_ctx->res_sfd_output_buffer,
+ size,
+ "sfd output buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+
+ i965_free_gpe_resource(&avc_ctx->res_sfd_cost_table_p_frame_buffer);
+ size = ALIGN(52,64);
+ allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
+&avc_ctx->res_sfd_cost_table_p_frame_buffer,
+ size,
+ "sfd P frame cost table buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+ data =
i965_map_gpe_resource(&(avc_ctx->res_sfd_cost_table_p_frame_buffer));
+ assert(data);
+ memcpy(data,gen9_avc_sfd_cost_table_p_frame,sizeof(unsigned char) *52);
+ i965_unmap_gpe_resource(&(avc_ctx->res_sfd_cost_table_p_frame_buffer));
+
+ i965_free_gpe_resource(&avc_ctx->res_sfd_cost_table_b_frame_buffer);
+ size = ALIGN(52,64);
+ allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
+&avc_ctx->res_sfd_cost_table_b_frame_buffer,
+ size,
+ "sfd B frame cost table buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+ data =
i965_map_gpe_resource(&(avc_ctx->res_sfd_cost_table_b_frame_buffer));
+ assert(data);
+ memcpy(data,gen9_avc_sfd_cost_table_b_frame,sizeof(unsigned char) *52);
+ i965_unmap_gpe_resource(&(avc_ctx->res_sfd_cost_table_b_frame_buffer));
+ }
+
+ /* wp related surfaces */
+ if(avc_state->weighted_prediction_supported)
+ {
+ for(i = 0; i< 2 ; i++)
+ {
+ if (avc_ctx->wp_output_pic_select_surface_obj[i]) {
+ continue;
+ }
+
+ width = generic_state->frame_width_in_pixel;
+ height= generic_state->frame_height_in_pixel ;
+ i965_CreateSurfaces(ctx,
+ width,
+ height,
+ VA_RT_FORMAT_YUV420,
+ 1,
+&avc_ctx->wp_output_pic_select_surface_id[i]);
+ avc_ctx->wp_output_pic_select_surface_obj[i] =
SURFACE(avc_ctx->wp_output_pic_select_surface_id[i]);
+
+ if (!avc_ctx->wp_output_pic_select_surface_obj[i]) {
+ goto failed_allocation;
+ }
+
+ i965_check_alloc_surface_bo(ctx,
avc_ctx->wp_output_pic_select_surface_obj[i], 1,
+ VA_FOURCC('N', 'V', '1', '2'),
SUBSAMPLE_YUV420);
+ }
+
i965_free_gpe_resource(&avc_ctx->res_wp_output_pic_select_surface_list[0]);
+
i965_object_surface_to_2d_gpe_resource_with_align(&avc_ctx->res_wp_output_pic_select_surface_list[0],
avc_ctx->wp_output_pic_select_surface_obj[0]);
+
i965_free_gpe_resource(&avc_ctx->res_wp_output_pic_select_surface_list[1]);
+
i965_object_surface_to_2d_gpe_resource_with_align(&avc_ctx->res_wp_output_pic_select_surface_list[1],
avc_ctx->wp_output_pic_select_surface_obj[1]);
+ }
+
+ /* other */
+
+ i965_free_gpe_resource(&avc_ctx->res_mad_data_buffer);
+ size = 4 * 1;
+ allocate_flag = i965_allocate_gpe_resource(i965->intel.bufmgr,
+&avc_ctx->res_mad_data_buffer,
+ ALIGN(size,0x1000),
+ "MAD data buffer");
+ if (!allocate_flag)
+ goto failed_allocation;
+
+ return VA_STATUS_SUCCESS;
+
+failed_allocation:
+ return VA_STATUS_ERROR_ALLOCATION_FAILED;
+}
+/*
+sfd related function
+*/
+static void
+gen9_avc_set_curbe_sfd(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void * param)
+{
+ gen9_avc_sfd_curbe_data *cmd;
+ struct encoder_vme_mfc_context * vme_context = (struct
encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct generic_enc_codec_state * generic_state = (struct
generic_enc_codec_state * )vme_context->generic_enc_state;
+ struct avc_enc_state * avc_state = (struct avc_enc_state *
)vme_context->private_enc_state;
+ VAEncSliceParameterBufferH264 * slice_param = avc_state->slice_param[0];
+
+ cmd = i965_gpe_context_map_curbe(gpe_context);
+
+ if (!cmd)
+ return;
+ memset(cmd,0,sizeof(gen9_avc_sfd_curbe_data));
+
+ cmd->dw0.enable_intra_cost_scaling_for_static_frame = 1 ;
+ cmd->dw0.enable_adaptive_mv_stream_in = 0 ; //vdenc
+ cmd->dw0.stream_in_type = 7 ; //vdenc
+ cmd->dw1.qp_value = avc_state->pic_param->pic_init_qp +
slice_param->slice_qp_delta ;
+
+ cmd->dw2.frame_width_in_mbs = generic_state->frame_width_in_mbs ;
+ cmd->dw2.frame_height_in_mbs = generic_state->frame_height_in_mbs ;
+
+ cmd->dw3.large_mv_threshold = 128 ;
+ cmd->dw4.total_large_mv_threshold = (generic_state->frame_width_in_mbs *
generic_state->frame_height_in_mbs)/100 ;
+ cmd->dw5.zmv_threshold = 4 ;
+ cmd->dw6.total_zmv_threshold = (generic_state->frame_width_in_mbs *
generic_state->frame_height_in_mbs * avc_state->zero_mv_threshold)/100 ; //
zero_mv_threshold = 60;
+ cmd->dw7.min_dist_threshold = 10 ;
+
+ if(generic_state->frame_type == SLICE_TYPE_P)
+ {
+ memcpy(cmd->cost_table,gen9_avc_sfd_cost_table_p_frame,52*
sizeof(unsigned char));
+
+ }else if(generic_state->frame_type == SLICE_TYPE_B)
+ {
+ memcpy(cmd->cost_table,gen9_avc_sfd_cost_table_b_frame,52*
sizeof(unsigned char));
+ }
+
+ cmd->dw21.actual_width_in_mb = cmd->dw2.frame_width_in_mbs ;
+ cmd->dw21.actual_height_in_mb = cmd->dw2.frame_height_in_mbs ;
+ cmd->dw24.vdenc_input_image_state_index =
GEN9_AVC_SFD_VDENC_INPUT_IMAGE_STATE_INDEX ;
+ cmd->dw26.mv_data_surface_index = GEN9_AVC_SFD_MV_DATA_SURFACE_INDEX ;
+ cmd->dw27.inter_distortion_surface_index =
GEN9_AVC_SFD_INTER_DISTORTION_SURFACE_INDEX ;
+ cmd->dw28.output_data_surface_index =
GEN9_AVC_SFD_OUTPUT_DATA_SURFACE_INDEX ;
+ cmd->dw29.vdenc_output_image_state_index =
GEN9_AVC_SFD_VDENC_OUTPUT_IMAGE_STATE_INDEX ;
+
+ i965_gpe_context_unmap_curbe(gpe_context);
+
+}
+
+static void
+gen9_avc_send_surface_sfd(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct i965_gpe_context *gpe_context,
+ struct intel_encoder_context *encoder_context,
+ void * param)
+{
+ struct encoder_vme_mfc_context * vme_context = (struct
encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context
* )vme_context->private_enc_ctx;
+ struct i965_gpe_resource *gpe_resource;
+ int size = 0;
+
+ /*HME mv data surface memv output 4x*/
+ gpe_resource =&avc_ctx->s4x_memv_data_buffer;
+ gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
+ gpe_resource,
+ 1,
+ I965_SURFACEFORMAT_R8_UNORM,
+ GEN9_AVC_SFD_MV_DATA_SURFACE_INDEX);
+
+ /* memv distortion */
+ gpe_resource =&avc_ctx->s4x_memv_distortion_buffer;
+ gen9_add_buffer_2d_gpe_surface(ctx, gpe_context,
+ gpe_resource,
+ 1,
+ I965_SURFACEFORMAT_R8_UNORM,
+
GEN9_AVC_SFD_INTER_DISTORTION_SURFACE_INDEX);
+ /*buffer output*/
+ size = 32 * 4 *4;
+ gpe_resource =&avc_ctx->res_sfd_output_buffer;
+ gen9_add_buffer_gpe_surface(ctx,
+ gpe_context,
+ gpe_resource,
+ 0,
+ size / 4,
+ 0,
+ GEN9_AVC_SFD_OUTPUT_DATA_SURFACE_INDEX);
+
+}
+
+static VAStatus
+gen9_avc_kernel_sfd(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ struct encoder_vme_mfc_context * vme_context = (struct
encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context
* )vme_context->private_enc_ctx;
+ struct generic_encoder_context * generic_ctx = (struct
generic_encoder_context * )vme_context->generic_enc_ctx;
+
+ struct i965_gpe_context *gpe_context;
+ struct gpe_media_object_parameter media_object_param;
+ struct gpe_media_object_inline_data media_object_inline_data;
+ int media_function = INTEL_MEDIA_STATE_STATIC_FRAME_DETECTION;
+ gpe_context =&(avc_ctx->context_sfd.gpe_contexts);
+
+ gen8_gpe_context_init(ctx, gpe_context);
+ gen9_gpe_reset_binding_table(ctx, gpe_context);
+
+ /*set curbe*/
+
generic_ctx->pfn_set_curbe_sfd(ctx,encode_state,gpe_context,encoder_context,NULL);
+
+ /*send surface*/
+
generic_ctx->pfn_send_sfd_surface(ctx,encode_state,gpe_context,encoder_context,NULL);
+
+ gen8_gpe_setup_interface_data(ctx, gpe_context);
+
+ memset(&media_object_param, 0, sizeof(media_object_param));
+ memset(&media_object_inline_data, 0, sizeof(media_object_inline_data));
+ media_object_param.pinline_data =&media_object_inline_data;
+ media_object_param.inline_size = sizeof(media_object_inline_data);
+
+ gen9_avc_run_kernel_media_object(ctx, encoder_context,
+ gpe_context,
+ media_function,
+&media_object_param);
+
+ return VA_STATUS_SUCCESS;
+}
+
+/*
+kernel related function:init/destroy etc
+*/
+static void
+gen9_avc_kernel_init_scaling(VADriverContextP ctx,
+ struct generic_encoder_context *generic_context,
+ struct gen9_avc_scaling_context *kernel_context)
+{
+ struct i965_gpe_context *gpe_context = NULL;
+ struct encoder_kernel_parameter kernel_param ;
+ struct encoder_scoreboard_parameter scoreboard_param;
+ struct i965_kernel common_kernel;
+
+ /* 4x scaling kernel*/
+ kernel_param.curbe_size = sizeof(gen9_avc_scaling4x_curbe_data);
+ kernel_param.inline_data_size = sizeof(gen9_avc_scaling4x_curbe_data);
+ kernel_param.sampler_size = 0;
+
+ memset(&scoreboard_param, 0, sizeof(scoreboard_param));
+ scoreboard_param.mask = 0xFF;
+ scoreboard_param.enable = generic_context->use_hw_scoreboard;
+ scoreboard_param.type = generic_context->use_hw_non_stalling_scoreboard;
+ scoreboard_param.walkpat_flag = 0;
+
+ gpe_context =&kernel_context->gpe_contexts[GEN9_AVC_KERNEL_SCALING_4X_IDX];
+ gen9_init_gpe_context_avc(ctx, gpe_context,&kernel_param);
+ gen9_init_vfe_scoreboard_avc(gpe_context,&scoreboard_param);
+
+ memset(&common_kernel, 0, sizeof(common_kernel));
+
+ intel_avc_get_kernel_header_and_size((void
*)(generic_context->enc_kernel_ptr),
+ generic_context->enc_kernel_size,
+ INTEL_GENERIC_ENC_SCALING4X,
+ 0,
+&common_kernel);
+
+ gen8_gpe_load_kernels(ctx,
+ gpe_context,
+&common_kernel,
+ 1);
+
+ /*2x scaling kernel*/
+ kernel_param.curbe_size = sizeof(gen9_avc_scaling2x_curbe_data);
+ kernel_param.inline_data_size = 0;
+ kernel_param.sampler_size = 0;
+
+ gpe_context =&kernel_context->gpe_contexts[GEN9_AVC_KERNEL_SCALING_2X_IDX];
+ gen9_init_gpe_context_avc(ctx, gpe_context,&kernel_param);
+ gen9_init_vfe_scoreboard_avc(gpe_context,&scoreboard_param);
+
+ memset(&common_kernel, 0, sizeof(common_kernel));
+
+ intel_avc_get_kernel_header_and_size((void
*)(generic_context->enc_kernel_ptr),
+ generic_context->enc_kernel_size,
+ INTEL_GENERIC_ENC_SCALING2X,
+ 0,
+&common_kernel);
+
+ gen8_gpe_load_kernels(ctx,
+ gpe_context,
+&common_kernel,
+ 1);
+
+}
+
+static void
+gen9_avc_kernel_init_me(VADriverContextP ctx,
+ struct generic_encoder_context *generic_context,
+ struct gen9_avc_me_context *kernel_context)
+{
+ struct i965_gpe_context *gpe_context = NULL;
+ struct encoder_kernel_parameter kernel_param ;
+ struct encoder_scoreboard_parameter scoreboard_param;
+ struct i965_kernel common_kernel;
+ int i = 0;
+
+ kernel_param.curbe_size = sizeof(gen9_avc_me_curbe_data);
+ kernel_param.inline_data_size = 0;
+ kernel_param.sampler_size = 0;
+
+ memset(&scoreboard_param, 0, sizeof(scoreboard_param));
+ scoreboard_param.mask = 0xFF;
+ scoreboard_param.enable = generic_context->use_hw_scoreboard;
+ scoreboard_param.type = generic_context->use_hw_non_stalling_scoreboard;
+ scoreboard_param.walkpat_flag = 0;
+
+ for (i = 0; i< 2; i++) {
+ gpe_context =&kernel_context->gpe_contexts[i];
+ gen9_init_gpe_context_avc(ctx, gpe_context,&kernel_param);
+ gen9_init_vfe_scoreboard_avc(gpe_context,&scoreboard_param);
+
+ memset(&common_kernel, 0, sizeof(common_kernel));
+
+ intel_avc_get_kernel_header_and_size((void
*)(generic_context->enc_kernel_ptr),
+ generic_context->enc_kernel_size,
+ INTEL_GENERIC_ENC_ME,
+ i,
+&common_kernel);
+
+ gen8_gpe_load_kernels(ctx,
+ gpe_context,
+&common_kernel,
+ 1);
+ }
+
+}
+
+static void
+gen9_avc_kernel_init_mbenc(VADriverContextP ctx,
+ struct generic_encoder_context *generic_context,
+ struct gen9_avc_mbenc_context *kernel_context)
+{
+ struct i965_gpe_context *gpe_context = NULL;
+ struct encoder_kernel_parameter kernel_param ;
+ struct encoder_scoreboard_parameter scoreboard_param;
+ struct i965_kernel common_kernel;
+ int i = 0;
+
+ kernel_param.curbe_size = sizeof(gen9_avc_mbenc_curbe_data);
+ kernel_param.inline_data_size = 0;
+ kernel_param.sampler_size = 0;
+
+ memset(&scoreboard_param, 0, sizeof(scoreboard_param));
+ scoreboard_param.mask = 0xFF;
+ scoreboard_param.enable = generic_context->use_hw_scoreboard;
+ scoreboard_param.type = generic_context->use_hw_non_stalling_scoreboard;
+ scoreboard_param.walkpat_flag = 0;
+
+ for (i = 0; i< NUM_GEN9_AVC_KERNEL_MBENC ; i++) {
+ gpe_context =&kernel_context->gpe_contexts[i];
+ gen9_init_gpe_context_avc(ctx, gpe_context,&kernel_param);
+ gen9_init_vfe_scoreboard_avc(gpe_context,&scoreboard_param);
+
+ memset(&common_kernel, 0, sizeof(common_kernel));
+
+ intel_avc_get_kernel_header_and_size((void
*)(generic_context->enc_kernel_ptr),
+ generic_context->enc_kernel_size,
+ INTEL_GENERIC_ENC_MBENC,
+ i,
+&common_kernel);
+
+ gen8_gpe_load_kernels(ctx,
+ gpe_context,
+&common_kernel,
+ 1);
+ }
+
+}
+
+static void
+gen9_avc_kernel_init_brc(VADriverContextP ctx,
+ struct generic_encoder_context *generic_context,
+ struct gen9_avc_brc_context *kernel_context)
+{
+ struct i965_gpe_context *gpe_context = NULL;
+ struct encoder_kernel_parameter kernel_param ;
+ struct encoder_scoreboard_parameter scoreboard_param;
+ struct i965_kernel common_kernel;
+ int i = 0;
+
+ static const int brc_curbe_size[NUM_GEN9_AVC_KERNEL_BRC] = {
+ (sizeof(gen9_avc_brc_init_reset_curbe_data)),
+ (sizeof(gen9_avc_frame_brc_update_curbe_data)),
+ (sizeof(gen9_avc_brc_init_reset_curbe_data)),
+ (sizeof(gen9_avc_mbenc_curbe_data)),
+ 0,
+ (sizeof(gen9_avc_mb_brc_curbe_data))
+ };
+
+ kernel_param.inline_data_size = 0;
+ kernel_param.sampler_size = 0;
+
+ memset(&scoreboard_param, 0, sizeof(scoreboard_param));
+ scoreboard_param.mask = 0xFF;
+ scoreboard_param.enable = generic_context->use_hw_scoreboard;
+ scoreboard_param.type = generic_context->use_hw_non_stalling_scoreboard;
+ scoreboard_param.walkpat_flag = 0;
+
+ for (i = 0; i< NUM_GEN9_AVC_KERNEL_BRC; i++) {
+ kernel_param.curbe_size = brc_curbe_size[i];
+ gpe_context =&kernel_context->gpe_contexts[i];
+ gen9_init_gpe_context_avc(ctx, gpe_context,&kernel_param);
+ gen9_init_vfe_scoreboard_avc(gpe_context,&scoreboard_param);
+
+ memset(&common_kernel, 0, sizeof(common_kernel));
+
+ intel_avc_get_kernel_header_and_size((void
*)(generic_context->enc_kernel_ptr),
+ generic_context->enc_kernel_size,
+ INTEL_GENERIC_ENC_BRC,
+ i,
+&common_kernel);
+
+ gen8_gpe_load_kernels(ctx,
+ gpe_context,
+&common_kernel,
+ 1);
+ }
+
+}
+
+static void
+gen9_avc_kernel_init_wp(VADriverContextP ctx,
+ struct generic_encoder_context *generic_context,
+ struct gen9_avc_wp_context *kernel_context)
+{
+ struct i965_gpe_context *gpe_context = NULL;
+ struct encoder_kernel_parameter kernel_param ;
+ struct encoder_scoreboard_parameter scoreboard_param;
+ struct i965_kernel common_kernel;
+
+ kernel_param.curbe_size = sizeof(gen9_avc_wp_curbe_data);
+ kernel_param.inline_data_size = 0;
+ kernel_param.sampler_size = 0;
+
+ memset(&scoreboard_param, 0, sizeof(scoreboard_param));
+ scoreboard_param.mask = 0xFF;
+ scoreboard_param.enable = generic_context->use_hw_scoreboard;
+ scoreboard_param.type = generic_context->use_hw_non_stalling_scoreboard;
+ scoreboard_param.walkpat_flag = 0;
+
+ gpe_context =&kernel_context->gpe_contexts;
+ gen9_init_gpe_context_avc(ctx, gpe_context,&kernel_param);
+ gen9_init_vfe_scoreboard_avc(gpe_context,&scoreboard_param);
+
+ memset(&common_kernel, 0, sizeof(common_kernel));
+
+ intel_avc_get_kernel_header_and_size((void
*)(generic_context->enc_kernel_ptr),
+ generic_context->enc_kernel_size,
+ INTEL_GENERIC_ENC_WP,
+ 0,
+&common_kernel);
+
+ gen8_gpe_load_kernels(ctx,
+ gpe_context,
+&common_kernel,
+ 1);
+
+}
+
+static void
+gen9_avc_kernel_init_sfd(VADriverContextP ctx,
+ struct generic_encoder_context *generic_context,
+ struct gen9_avc_sfd_context *kernel_context)
+{
+ struct i965_gpe_context *gpe_context = NULL;
+ struct encoder_kernel_parameter kernel_param ;
+ struct encoder_scoreboard_parameter scoreboard_param;
+ struct i965_kernel common_kernel;
+
+ kernel_param.curbe_size = sizeof(gen9_avc_sfd_curbe_data);
+ kernel_param.inline_data_size = 0;
+ kernel_param.sampler_size = 0;
+
+ memset(&scoreboard_param, 0, sizeof(scoreboard_param));
+ scoreboard_param.mask = 0xFF;
+ scoreboard_param.enable = generic_context->use_hw_scoreboard;
+ scoreboard_param.type = generic_context->use_hw_non_stalling_scoreboard;
+ scoreboard_param.walkpat_flag = 0;
+
+ gpe_context =&kernel_context->gpe_contexts;
+ gen9_init_gpe_context_avc(ctx, gpe_context,&kernel_param);
+ gen9_init_vfe_scoreboard_avc(gpe_context,&scoreboard_param);
+
+ memset(&common_kernel, 0, sizeof(common_kernel));
+
+ intel_avc_get_kernel_header_and_size((void
*)(generic_context->enc_kernel_ptr),
+ generic_context->enc_kernel_size,
+ INTEL_GENERIC_ENC_SFD,
+ 0,
+&common_kernel);
+
+ gen8_gpe_load_kernels(ctx,
+ gpe_context,
+&common_kernel,
+ 1);
+
+}
+
+static void
+gen9_avc_kernel_destroy(struct encoder_vme_mfc_context * vme_context)
+{
+
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context
* )vme_context->private_enc_ctx;
+
+ int i = 0;
+
+ gen9_avc_free_resources(vme_context);
+
+ for(i = 0; i< NUM_GEN9_AVC_KERNEL_SCALING; i++)
+ gen8_gpe_context_destroy(&avc_ctx->context_scaling.gpe_contexts[i]);
+
+ for(i = 0; i< NUM_GEN9_AVC_KERNEL_BRC; i++)
+ gen8_gpe_context_destroy(&avc_ctx->context_brc.gpe_contexts[i]);
+
+ for(i = 0; i< NUM_GEN9_AVC_KERNEL_ME; i++)
+ gen8_gpe_context_destroy(&avc_ctx->context_me.gpe_contexts[i]);
+
+ for(i = 0; i< NUM_GEN9_AVC_KERNEL_MBENC; i++)
+ gen8_gpe_context_destroy(&avc_ctx->context_mbenc.gpe_contexts[i]);
+
+ gen8_gpe_context_destroy(&avc_ctx->context_wp.gpe_contexts);
+
+ gen8_gpe_context_destroy(&avc_ctx->context_sfd.gpe_contexts);
+
+}
+
+ if(generic_state->window_size == 0)
+ {
+ generic_state->window_size = (generic_state->frames_per_100s/100<
60)?(generic_state->frames_per_100s/100):60;
+ }else if(generic_state->window_size> 2 *
generic_state->frames_per_100s/100)
+ {
+ generic_state->window_size = (generic_state->frames_per_100s/100<
60)?(generic_state->frames_per_100s/100):60;
+ }
+ avc_state->top_field_poc[2*i] =
avc_priv_surface->top_field_order_cnt;
+ avc_state->top_field_poc[2*i+1] =
avc_priv_surface->top_field_order_cnt + 1;
+ avc_priv_surface->frame_store_id = i;
+ }else
+ {
+ break;
+ }
+ }
+
+ /* Encoded bitstream ?*/
+ obj_buffer = encode_state->coded_buf_object;
+ bo = obj_buffer->buffer_store->bo;
+ i965_free_gpe_resource(&generic_ctx->compressed_bitstream.res);
+
i965_dri_object_to_buffer_gpe_resource(&generic_ctx->compressed_bitstream.res,
bo);
+ generic_ctx->compressed_bitstream.start_offset =
I965_CODEDBUFFER_HEADER_SIZE;
+ generic_ctx->compressed_bitstream.end_offset =
ALIGN(obj_buffer->size_element - 0x1000, 0x1000);
+
+ /*status buffer */
+ avc_ctx->status_buffer.bo = bo;
+
+ /* set the internal flag to 0 to indicate the coded size is unknown */
+ dri_bo_map(bo, 1);
+ coded_buffer_segment = (struct i965_coded_buffer_segment *)bo->virtual;
+ coded_buffer_segment->mapped = 0;
+ coded_buffer_segment->codec = encoder_context->codec;
+ coded_buffer_segment->status_support = 1;
+
+ pdata = bo->virtual + avc_ctx->status_buffer.base_offset;
+ memset(pdata,0,avc_ctx->status_buffer.status_buffer_size);
+ dri_bo_unmap(bo);
+
+ //frame id, it is the ref pic id in the reference_objects list.
+ avc_state->num_refs[0] = 0;
+ avc_state->num_refs[1] = 0;
+ if (generic_state->frame_type == SLICE_TYPE_P) {
+ avc_state->num_refs[0] = pic_param->num_ref_idx_l0_active_minus1 + 1;
+
+ if (slice_param->num_ref_idx_active_override_flag)
+ avc_state->num_refs[0] = slice_param->num_ref_idx_l0_active_minus1
+ 1;
+ } else if (generic_state->frame_type == SLICE_TYPE_B) {
+ avc_state->num_refs[0] = pic_param->num_ref_idx_l0_active_minus1 + 1;
+ avc_state->num_refs[1] = pic_param->num_ref_idx_l1_active_minus1 + 1;
+
+ if (slice_param->num_ref_idx_active_override_flag) {
+ avc_state->num_refs[0] = slice_param->num_ref_idx_l0_active_minus1
+ 1;
+ avc_state->num_refs[1] = slice_param->num_ref_idx_l1_active_minus1
+ 1;
+ }
+ }
+
+ if (avc_state->num_refs[0]> ARRAY_ELEMS(avc_state->list_ref_idx[0]))
+ return VA_STATUS_ERROR_INVALID_VALUE;
+ if (avc_state->num_refs[1]> ARRAY_ELEMS(avc_state->list_ref_idx[1]))
+ return VA_STATUS_ERROR_INVALID_VALUE;
+
+ for (i = 0; i< ARRAY_ELEMS(avc_state->list_ref_idx[0]); i++) {
+ VAPictureH264 *va_pic;
+
+ assert(ARRAY_ELEMS(slice_param->RefPicList0) ==
ARRAY_ELEMS(avc_state->list_ref_idx[0]));
+ avc_state->list_ref_idx[0][i] = 0;
+
+ if (i>= avc_state->num_refs[0])
+ continue;
+
+ va_pic =&slice_param->RefPicList0[i];
+
+ for (j = 0; j< ARRAY_ELEMS(encode_state->reference_objects); j++) {
+ obj_surface = encode_state->reference_objects[j];
+
+ if (obj_surface&&
+ obj_surface->bo&&
+ obj_surface->base.id == va_pic->picture_id) {
+
+ assert(obj_surface->base.id != VA_INVALID_SURFACE);
+ avc_state->list_ref_idx[0][i] = j;
+
+ break;
+ }
+ }
+ }
+ for (i = 0; i< ARRAY_ELEMS(avc_state->list_ref_idx[1]); i++) {
+ VAPictureH264 *va_pic;
+
+ assert(ARRAY_ELEMS(slice_param->RefPicList1) ==
ARRAY_ELEMS(avc_state->list_ref_idx[1]));
+ avc_state->list_ref_idx[1][i] = 0;
+
+ if (i>= avc_state->num_refs[1])
+ continue;
+
+ va_pic =&slice_param->RefPicList1[i];
+
+ for (j = 0; j< ARRAY_ELEMS(encode_state->reference_objects); j++) {
+ obj_surface = encode_state->reference_objects[j];
+
+ if (obj_surface&&
+ obj_surface->bo&&
+ obj_surface->base.id == va_pic->picture_id) {
+
+ assert(obj_surface->base.id != VA_INVALID_SURFACE);
+ avc_state->list_ref_idx[1][i] = j;
+
+ break;
+ }
+ }
+ }
+
+ return VA_STATUS_SUCCESS;
+}
+
+static VAStatus
+gen9_avc_vme_gpe_kernel_init(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ return VA_STATUS_SUCCESS;
+}
+
+static VAStatus
+gen9_avc_vme_gpe_kernel_final(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+
+ struct encoder_vme_mfc_context * vme_context = (struct
encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct generic_enc_codec_state * generic_state = (struct
generic_enc_codec_state * )vme_context->generic_enc_state;
+ struct avc_enc_state * avc_state = (struct avc_enc_state *
)vme_context->private_enc_state;
+
+ /*set this flag when all kernel is finished*/
+ if(generic_state->brc_enabled)
+ {
+ generic_state->brc_inited = 1;
+ generic_state->brc_need_reset = 0;
+ avc_state->mbenc_curbe_set_in_brc_update = 0;
+ }
+ return VA_STATUS_SUCCESS;
+}
+
+static VAStatus
+gen9_avc_vme_gpe_kernel_run(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ struct encoder_vme_mfc_context * vme_context = (struct
encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct generic_enc_codec_state * generic_state = (struct
generic_enc_codec_state * )vme_context->generic_enc_state;
+ struct avc_enc_state * avc_state = (struct avc_enc_state *
)vme_context->private_enc_state;
+
+ VAEncPictureParameterBufferH264 *pic_param = avc_state->pic_param;
+ VAEncSliceParameterBufferH264 *slice_param = avc_state->slice_param[0];
+ int sfd_in_use = 0;
+
+ /* BRC init/reset needs to be called before HME since it will reset the
Brc Distortion surface*/
+ if(generic_state->brc_enabled&&(!generic_state->brc_inited ||
generic_state->brc_need_reset ))
+ {
+ gen9_avc_kernel_brc_init_reset(ctx,encode_state,encoder_context);
+ }
+
+ /*down scaling*/
+ if(generic_state->hme_supported)
+ {
+
gen9_avc_kernel_scaling(ctx,encode_state,encoder_context,INTEL_ENC_HME_4x);
+ if(generic_state->b16xme_supported)
+ {
+
gen9_avc_kernel_scaling(ctx,encode_state,encoder_context,INTEL_ENC_HME_16x);
+ if(generic_state->b32xme_supported)
+ {
+
gen9_avc_kernel_scaling(ctx,encode_state,encoder_context,INTEL_ENC_HME_32x);
+ }
+ }
+ }
+
+ /*me kernel*/
+ if(generic_state->hme_enabled)
+ {
+ if(generic_state->b16xme_enabled)
+ {
+ if(generic_state->b32xme_enabled)
+ {
+
gen9_avc_kernel_me(ctx,encode_state,encoder_context,INTEL_ENC_HME_32x);
+ }
+
gen9_avc_kernel_me(ctx,encode_state,encoder_context,INTEL_ENC_HME_16x);
+ }
+ gen9_avc_kernel_me(ctx,encode_state,encoder_context,INTEL_ENC_HME_4x);
+ }
+
+ /*call SFD kernel after HME in same command buffer*/
+ sfd_in_use = avc_state->sfd_enable&& generic_state->hme_enabled;
+ sfd_in_use = sfd_in_use&& !avc_state->sfd_mb_enable;
+ if(sfd_in_use)
+ {
+ gen9_avc_kernel_sfd(ctx,encode_state,encoder_context);
+ }
+
+ /* BRC and MbEnc are included in the same task phase*/
+ if(generic_state->brc_enabled)
+ {
+ if(avc_state->mbenc_i_frame_dist_in_use)
+ {
+ gen9_avc_kernel_mbenc(ctx,encode_state,encoder_context,true);
+ }
+ gen9_avc_kernel_brc_frame_update(ctx,encode_state,encoder_context);
+
+ if(generic_state->mb_brc_enabled)
+ {
+ gen9_avc_kernel_brc_mb_update(ctx,encode_state,encoder_context);
+ }
+ }
+
+ /*weight prediction,disable by now */
+ avc_state->weighted_ref_l0_enable = 0;
+ avc_state->weighted_ref_l1_enable = 0;
+ if(avc_state->weighted_prediction_supported&&
+ ((generic_state->frame_type == SLICE_TYPE_P&&
pic_param->pic_fields.bits.weighted_pred_flag) ||
+ (generic_state->frame_type == SLICE_TYPE_B&&
pic_param->pic_fields.bits.weighted_bipred_idc == INTEL_AVC_WP_MODE_EXPLICIT)))
+ {
+ if(slice_param->luma_weight_l0_flag& 1)
+ {
+ gen9_avc_kernel_wp(ctx,encode_state,encoder_context,0);
+
+ }else if(!(slice_param->chroma_weight_l0_flag& 1))
+ {
+ pic_param->pic_fields.bits.weighted_pred_flag = 0;// it should be
handled in app
+ }
+
+ if(generic_state->frame_type == SLICE_TYPE_B&&
pic_param->pic_fields.bits.weighted_bipred_idc == INTEL_AVC_WP_MODE_EXPLICIT)
+ {
+ if(slice_param->luma_weight_l1_flag& 1)
+ {
+ gen9_avc_kernel_wp(ctx,encode_state,encoder_context,1);
+ }else if(!((slice_param->luma_weight_l0_flag& 1)||
+ (slice_param->chroma_weight_l0_flag& 1)||
+ (slice_param->chroma_weight_l1_flag& 1)))
+ {
+ pic_param->pic_fields.bits.weighted_bipred_idc =
INTEL_AVC_WP_MODE_DEFAULT;// it should be handled in app
+ }
+ }
+ }
+
+ /*mbenc kernel*/
+ gen9_avc_kernel_mbenc(ctx,encode_state,encoder_context,false);
+
+ /*ignore the reset vertical line kernel*/
+
+ return VA_STATUS_SUCCESS;
+}
+
+static VAStatus
+gen9_avc_vme_pipeline(VADriverContextP ctx,
+ VAProfile profile,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context)
+{
+ VAStatus va_status;
+
+ gen9_avc_update_parameters(ctx, profile, encode_state, encoder_context);
+
+ va_status = gen9_avc_encode_check_parameter(ctx, encode_state,
encoder_context);
+ if (va_status != VA_STATUS_SUCCESS)
+ return va_status;
+
+ va_status = gen9_avc_allocate_resources(ctx, encode_state,
encoder_context);
+ if (va_status != VA_STATUS_SUCCESS)
+ return va_status;
+
+ va_status = gen9_avc_vme_gpe_kernel_prepare(ctx, encode_state,
encoder_context);
+ if (va_status != VA_STATUS_SUCCESS)
+ return va_status;
+
+ va_status = gen9_avc_vme_gpe_kernel_init(ctx, encode_state,
encoder_context);
+ if (va_status != VA_STATUS_SUCCESS)
+ return va_status;
+
+ va_status = gen9_avc_vme_gpe_kernel_run(ctx, encode_state,
encoder_context);
+ if (va_status != VA_STATUS_SUCCESS)
+ return va_status;
+
+ gen9_avc_vme_gpe_kernel_final(ctx, encode_state, encoder_context);
+
+ return VA_STATUS_SUCCESS;
+}
+
+static void
+gen9_avc_vme_context_destroy(void * context)
+{
+ struct encoder_vme_mfc_context *vme_context = (struct
encoder_vme_mfc_context *)context;
+ struct generic_encoder_context * generic_ctx = (struct
generic_encoder_context * )vme_context->generic_enc_ctx;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context
* )vme_context->private_enc_ctx;
+ struct generic_enc_codec_state * generic_state = (struct
generic_enc_codec_state * )vme_context->generic_enc_state;
+ struct avc_enc_state * avc_state = (struct avc_enc_state *
)vme_context->private_enc_state;
+
+ if (!vme_context)
+ return;
+
+ gen9_avc_kernel_destroy(vme_context);
+
+ if(generic_ctx)
+ free(generic_ctx);
+
+ if(avc_ctx)
+ free(avc_ctx);
+
+ if(generic_state)
+ free(generic_state);
+
+ if(avc_state)
+ free(avc_state);
+
+ if(vme_context)
+ free(vme_context);
+ return;
+
+}
+
+static void
+gen9_avc_kernel_init(VADriverContextP ctx,
+ struct intel_encoder_context *encoder_context)
+{
+ struct encoder_vme_mfc_context * vme_context = (struct
encoder_vme_mfc_context *)encoder_context->vme_context;
+ struct gen9_avc_encoder_context * avc_ctx = (struct gen9_avc_encoder_context
* )vme_context->private_enc_ctx;
+ struct generic_encoder_context * generic_ctx = (struct
generic_encoder_context * )vme_context->generic_enc_ctx;
+
+ gen9_avc_kernel_init_scaling(ctx,generic_ctx,&avc_ctx->context_scaling);
+ gen9_avc_kernel_init_brc(ctx,generic_ctx,&avc_ctx->context_brc);
+ gen9_avc_kernel_init_me(ctx,generic_ctx,&avc_ctx->context_me);
+ gen9_avc_kernel_init_mbenc(ctx,generic_ctx,&avc_ctx->context_mbenc);
+ gen9_avc_kernel_init_wp(ctx,generic_ctx,&avc_ctx->context_wp);
+ gen9_avc_kernel_init_sfd(ctx,generic_ctx,&avc_ctx->context_sfd);
+
+ //function pointer
+ generic_ctx->pfn_set_curbe_scaling2x = gen9_avc_set_curbe_scaling2x;
+ generic_ctx->pfn_set_curbe_scaling4x = gen9_avc_set_curbe_scaling4x;
+ generic_ctx->pfn_set_curbe_me = gen9_avc_set_curbe_me;
+ generic_ctx->pfn_set_curbe_mbenc = gen9_avc_set_curbe_mbenc;
+ generic_ctx->pfn_set_curbe_brc_init_reset =
gen9_avc_set_curbe_brc_init_reset;
+ generic_ctx->pfn_set_curbe_brc_frame_update =
gen9_avc_set_curbe_brc_frame_update;
+ generic_ctx->pfn_set_curbe_brc_mb_update =
gen9_avc_set_curbe_brc_mb_update;
+ generic_ctx->pfn_set_curbe_sfd = gen9_avc_set_curbe_sfd;
+ generic_ctx->pfn_set_curbe_wp = gen9_avc_set_curbe_wp;
+
+ generic_ctx->pfn_send_scaling_surface = gen9_avc_send_surface_scaling;
+ generic_ctx->pfn_send_me_surface = gen9_avc_send_surface_me;
+ generic_ctx->pfn_send_mbenc_surface = gen9_avc_send_surface_mbenc;
+ generic_ctx->pfn_send_brc_init_reset_surface =
gen9_avc_send_surface_brc_init_reset;
+ generic_ctx->pfn_send_brc_frame_update_surface =
gen9_avc_send_surface_brc_frame_update;
+ generic_ctx->pfn_send_brc_mb_update_surface =
gen9_avc_send_surface_brc_mb_update;
+ generic_ctx->pfn_send_sfd_surface = gen9_avc_send_surface_sfd;
+ generic_ctx->pfn_send_wp_surface = gen9_avc_send_surface_wp;
+}
+
+Bool
+gen9_avc_vme_context_init(VADriverContextP ctx, struct intel_encoder_context
*encoder_context)
+{
+ /* VME& PAK share the same context */
+ struct i965_driver_data *i965 = i965_driver_data(ctx);
+ struct encoder_vme_mfc_context * vme_context = NULL;
+ struct generic_encoder_context * generic_ctx = NULL;
+ struct gen9_avc_encoder_context * avc_ctx = NULL;
+ struct generic_enc_codec_state * generic_state = NULL;
+ struct avc_enc_state * avc_state = NULL;
+ struct encoder_status_buffer_internal *status_buffer;
+ uint32_t base_offset = offsetof(struct i965_coded_buffer_segment,
codec_private_data);
+
+ vme_context = calloc(1, sizeof(struct encoder_vme_mfc_context));
+ generic_ctx = calloc(1, sizeof(struct generic_encoder_context));
+ avc_ctx = calloc(1, sizeof(struct gen9_avc_encoder_context));
+ generic_state = calloc(1, sizeof(struct generic_enc_codec_state));
+ avc_state = calloc(1, sizeof(struct avc_enc_state));
+
+ if(!vme_context || !generic_ctx || !avc_ctx || !generic_state ||
!avc_state)
+ goto allocate_structure_failed;
+
+ memset(vme_context,0,sizeof(struct encoder_vme_mfc_context));
+ memset(generic_ctx,0,sizeof(struct generic_encoder_context));
+ memset(avc_ctx,0,sizeof(struct gen9_avc_encoder_context));
+ memset(generic_state,0,sizeof(struct generic_enc_codec_state));
+ memset(avc_state,0,sizeof(struct avc_enc_state));
+
+ encoder_context->vme_context = vme_context;
+ vme_context->generic_enc_ctx = generic_ctx;
+ vme_context->private_enc_ctx = avc_ctx;
+ vme_context->generic_enc_state = generic_state;
+ vme_context->private_enc_state = avc_state;
+
+ if (IS_SKL(i965->intel.device_info)) {
+ generic_ctx->enc_kernel_ptr = (void *)skl_avc_encoder_kernels;
+ generic_ctx->enc_kernel_size = sizeof(skl_avc_encoder_kernels);
+ }
+ else
+ goto allocate_structure_failed;
+
+ /* initialize misc ? */
+ avc_ctx->ctx = ctx;
+ generic_ctx->use_hw_scoreboard = 1;
+ generic_ctx->use_hw_non_stalling_scoreboard = 1;
+
+ /* initialize generic state */
+
+ generic_state->kernel_mode = INTEL_ENC_KERNEL_NORMAL;
+ generic_state->preset = INTEL_PRESET_RT_SPEED;
+ generic_state->seq_frame_number = 0;
+ generic_state->total_frame_number = 0;
+ generic_state->frame_type = 0;
+ generic_state->first_frame = 1;
+
+ generic_state->frame_width_in_pixel = 0;
+ generic_state->frame_height_in_pixel = 0;
+ generic_state->frame_width_in_mbs = 0;
+ generic_state->frame_height_in_mbs = 0;
+ generic_state->frame_width_4x = 0;
+ generic_state->frame_height_4x = 0;
+ generic_state->frame_width_16x = 0;
+ generic_state->frame_height_16x = 0;
+ generic_state->frame_width_32x = 0;
+ generic_state->downscaled_width_4x_in_mb = 0;
+ generic_state->downscaled_height_4x_in_mb = 0;
+ generic_state->downscaled_width_16x_in_mb = 0;
+ generic_state->downscaled_height_16x_in_mb = 0;
+ generic_state->downscaled_width_32x_in_mb = 0;
+ generic_state->downscaled_height_32x_in_mb = 0;
+
+ generic_state->hme_supported = 1;
+ generic_state->b16xme_supported = 1;
+ generic_state->b32xme_supported = 0;
+ generic_state->hme_enabled = 0;
+ generic_state->b16xme_enabled = 0;
+ generic_state->b32xme_enabled = 0;
+ generic_state->brc_distortion_buffer_supported = 1;
+ generic_state->brc_constant_buffer_supported = 0;
+
+
+ generic_state->frame_rate = 30;
+ generic_state->brc_allocated = 0;
+ generic_state->brc_inited = 0;
+ generic_state->brc_need_reset = 0;
+ generic_state->is_low_delay = 0;
+ generic_state->brc_enabled = 0;//default
+ generic_state->internal_rate_mode = 0;
+ generic_state->curr_pak_pass = 0;
+ generic_state->num_pak_passes = MAX_AVC_PAK_PASS_NUM;
+ generic_state->is_first_pass = 1;
+ generic_state->is_last_pass = 0;
+ generic_state->mb_brc_enabled = 0; // enable mb brc
+ generic_state->brc_roi_enable = 0;
+ generic_state->brc_dirty_roi_enable = 0;
+ generic_state->skip_frame_enbale = 0;
+
+ generic_state->target_bit_rate = 0;
+ generic_state->max_bit_rate = 0;
+ generic_state->min_bit_rate = 0;
+ generic_state->init_vbv_buffer_fullness_in_bit = 0;
+ generic_state->vbv_buffer_size_in_bit = 0;
+ generic_state->frames_per_100s = 0;
+ generic_state->gop_size = 0;
+ generic_state->gop_ref_distance = 0;
+ generic_state->brc_target_size = 0;
+ generic_state->brc_mode = 0;
+ generic_state->brc_init_current_target_buf_full_in_bits = 0.0;
+ generic_state->brc_init_reset_input_bits_per_frame = 0.0;
+ generic_state->brc_init_reset_buf_size_in_bits = 0;
+ generic_state->brc_init_previous_target_buf_full_in_bits = 0;
+ generic_state->window_size = 0;//default
+ generic_state->target_percentage = 0;
+
+ generic_state->avbr_curracy = 0;
+ generic_state->avbr_convergence = 0;
+
+ generic_state->num_skip_frames = 0;
+ generic_state->size_skip_frames = 0;
+
+ generic_state->num_roi = 0;
+ generic_state->max_delta_qp = 0;
+ generic_state->min_delta_qp = 0;
+
+ if (encoder_context->rate_control_mode != VA_RC_NONE&&
+ encoder_context->rate_control_mode != VA_RC_CQP) {
+ generic_state->brc_enabled = 1;
+ generic_state->brc_distortion_buffer_supported = 1;
+ generic_state->brc_constant_buffer_supported = 1;
+ generic_state->num_pak_passes = MAX_AVC_PAK_PASS_NUM;
+ }
+ /*avc state initialization */
+ avc_state->mad_enable = 0;
+ avc_state->mb_disable_skip_map_enable = 0;
+ avc_state->sfd_enable = 1;//default
+ avc_state->sfd_mb_enable = 1;//set it true
+ avc_state->adaptive_search_window_enable = 1;//default
+ avc_state->mb_qp_data_enable = 0;
+ avc_state->intra_refresh_i_enable = 0;
+ avc_state->min_max_qp_enable = 0;
+ avc_state->skip_bias_adjustment_enable = 0;//default,same as
skip_bias_adjustment_supporte? no
+
+ //external input
+ avc_state->non_ftq_skip_threshold_lut_input_enable = 0;
+ avc_state->ftq_skip_threshold_lut_input_enable = 0;
+ avc_state->ftq_override = 0;
+
+ avc_state->direct_bias_adjustment_enable = 0;
+ avc_state->global_motion_bias_adjustment_enable = 0;
+ avc_state->disable_sub_mb_partion = 0;
+ avc_state->arbitrary_num_mbs_in_slice = 0;
+ avc_state->adaptive_transform_decision_enable = 0;//default
+ avc_state->skip_check_disable = 0;
+ avc_state->tq_enable = 0;
+ avc_state->enable_avc_ildb = 0;
+ avc_state->mbaff_flag = 0;
+ avc_state->enable_force_skip = 1;//default
+ avc_state->rc_panic_enable = 1;//default
+ avc_state->suppress_recon_enable = 1;//default
+
+ avc_state->ref_pic_select_list_supported = 1;
+ avc_state->mb_brc_supported = 1;//?,default
+ avc_state->multi_pre_enable = 1;//default
+ avc_state->ftq_enable = 1;//default
+ avc_state->caf_supported = 1; //default
+ avc_state->caf_enable = 0;
+ avc_state->caf_disable_hd = 1;//default
+ avc_state->skip_bias_adjustment_supported = 1;//default
+
+ avc_state->adaptive_intra_scaling_enable = 1;//default
+ avc_state->old_mode_cost_enable = 0;//default
+ avc_state->multi_ref_qp_enable = 1;//default
+ avc_state->weighted_ref_l0_enable = 1;//default
+ avc_state->weighted_ref_l1_enable = 1;//default
+ avc_state->weighted_prediction_supported = 0;
+ avc_state->brc_split_enable = 0;
+ avc_state->slice_level_report_supported = 0;
+
+ avc_state->fbr_bypass_enable = 1;//default
+ avc_state->field_scaling_output_interleaved = 0;
+ avc_state->mb_variance_output_enable = 0;
+ avc_state->mb_pixel_average_output_enable = 0;
+ avc_state->rolling_intra_refresh_enable = 0;// same as
intra_refresh_i_enable?
+ avc_state->mbenc_curbe_set_in_brc_update = 0;
+ avc_state->rounding_inter_enable = 1; //default
+ avc_state->adaptive_rounding_inter_enable = 1;//default
+
+ avc_state->mbenc_i_frame_dist_in_use = 0;
+ avc_state->mb_status_supported = 1; //set in intialization for gen9
+ avc_state->mb_status_enable = 0;
+ avc_state->mb_vproc_stats_enable = 0;
+ avc_state->flatness_check_enable = 0;
+ avc_state->flatness_check_supported = 1;//default
+ avc_state->block_based_skip_enable = 0;
+ avc_state->use_widi_mbenc_kernel = 0;
+ avc_state->kernel_trellis_enable = 0;
+ avc_state->generic_reserved = 0;
+
+ avc_state->rounding_value = 0;
+ avc_state->rounding_inter_p = 255;//default
+ avc_state->rounding_inter_b = 255; //default
+ avc_state->rounding_inter_b_ref = 255; //default
+ avc_state->min_qp_i = INTEL_AVC_MIN_QP;
+ avc_state->min_qp_p = INTEL_AVC_MIN_QP;
+ avc_state->min_qp_b = INTEL_AVC_MIN_QP;
+ avc_state->max_qp_i = INTEL_AVC_MAX_QP;
+ avc_state->max_qp_p = INTEL_AVC_MAX_QP;
+ avc_state->max_qp_b = INTEL_AVC_MAX_QP;
+
+ memset(avc_state->non_ftq_skip_threshold_lut,0,52*sizeof(uint8_t));
+ memset(avc_state->ftq_skip_threshold_lut,0,52*sizeof(uint8_t));
+ memset(avc_state->lamda_value_lut,0,52*2*sizeof(uint8_t));
+
+ avc_state->intra_refresh_qp_threshold = 0;
+ avc_state->trellis_flag = 0;
+ avc_state->hme_mv_cost_scaling_factor = 0;
+ avc_state->slice_height = 1;
+ avc_state->slice_num = 1;
+ memset(avc_state->dist_scale_factor_list0,0,32*sizeof(uint32_t));
+ avc_state->bi_weight = 0;
+ avc_state->brc_const_data_surface_width = 64;
+ avc_state->brc_const_data_surface_height = 44;
+
+ avc_state->num_refs[0] = 0;
+ avc_state->num_refs[1] = 0;
+ memset(avc_state->list_ref_idx,0,32*2*sizeof(uint32_t));
+ memset(avc_state->top_field_poc,0,NUM_MFC_AVC_DMV_BUFFERS*sizeof(int32_t));
+ avc_state->tq_rounding = 0;
+ avc_state->zero_mv_threshold = 0;
+ avc_state->slice_second_levle_batch_buffer_in_use = 0;
+
+ //1. seq/pic/slice
+
+ /* the definition of status buffer offset for Encoder */
+
+ status_buffer =&avc_ctx->status_buffer;
+ memset(status_buffer, 0,sizeof(struct encoder_status_buffer_internal));
+
+ status_buffer->base_offset = base_offset;
+ status_buffer->bs_byte_count_frame_offset = base_offset + offsetof(struct
encoder_status, bs_byte_count_frame);
+ status_buffer->bs_byte_count_frame_nh_offset = base_offset +
offsetof(struct encoder_status, bs_byte_count_frame_nh);
+ status_buffer->image_status_mask_offset = base_offset + offsetof(struct
encoder_status, image_status_mask);
+ status_buffer->image_status_ctrl_offset = base_offset + offsetof(struct
encoder_status, image_status_ctrl);
+ status_buffer->mfc_qp_status_count_offset = base_offset + offsetof(struct
encoder_status, mfc_qp_status_count);
+ status_buffer->media_index_offset = base_offset + offsetof(struct
encoder_status, media_index);
+
+ status_buffer->status_buffer_size = sizeof(struct encoder_status);
+ status_buffer->bs_byte_count_frame_reg_offset =
MFC_BITSTREAM_BYTECOUNT_FRAME_REG;
+ status_buffer->bs_byte_count_frame_nh_reg_offset =
MFC_BITSTREAM_BYTECOUNT_SLICE_REG;
+ status_buffer->image_status_mask_reg_offset = MFC_IMAGE_STATUS_MASK_REG;
+ status_buffer->image_status_ctrl_reg_offset = MFC_IMAGE_STATUS_CTRL_REG;
+ status_buffer->mfc_qp_status_count_reg_offset = MFC_QP_STATUS_COUNT_REG;
+
+ gen9_avc_kernel_init(ctx,encoder_context);
+ encoder_context->vme_context = vme_context;
+ encoder_context->vme_pipeline = gen9_avc_vme_pipeline;
+ encoder_context->vme_context_destroy = gen9_avc_vme_context_destroy;
+
+ return true;
+
+allocate_structure_failed:
+
+ if(vme_context)
+ free(vme_context);
+
+ if(generic_ctx)
+ free(generic_ctx);
+
+ if(avc_ctx)
+ free(avc_ctx);
+
+ if(generic_state)
+ free(generic_state);
+
+ if(avc_state)
+ free(avc_state);
+
+ return false;
+}
