== This week == * Spent about half of the week on auto increment/decrement. There are two execution failures left.
* Looked at assembly comparisons between the old pass and various forms of the new pass. The results look reasonable. * Ran DENbench and my libav microbenchmarks to measure the difference in performance. Saw that some tests were repeatably worse. * Looked into those tests and realised that they were being hit by the lack of an address writeback model in the scheduler (a known limitation). Dependent stores were being scheduled in a block at the end of the loop because we said that the dependencies had 0 latency. * Spent most of the rest of the week on fixing that limitation. One of the difficulties is that define_bypass currently requires a complete list of instruction reservations. This is difficult for things like writeback because the result could in principle be used by many different instructions. Decided to generalise define_bypass so that it can handle filename-style globs. * Wrote a patch to model writeback in NEON. * Wrote a patch to model writeback in core instructions. However, while doing this, I noticed that the behaviour I'm seeing on our Cortex-A8 doesn't match what I'd expected from GCC's A8 scheduler description (or the documentation). Talked with Ramana about it. Distilled a benchmark. * These scheduler changes didn't improve the DENbench and libav scores much by themselves, but the combination of the scheduler and auto inc/dec changes did produce noticeable improvements in some libav benchmarks and rather smaller improvements in some DENbench ones. == Next week == * Finish scheduler work, in light of observed behaviour. * More testing prior to submission. I'm away the week of 13th June. Richard _______________________________________________ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-toolchain
