Adjusted my 64-bit shifts patch to address Richard Earnshaw's concerns,
tested it, and posted the new one upstream.
Continued trying to figure out how ira-costs.c works, and in particular,
why it doesn't choose to do 64-bit stuff in NEON when I think it should.
Basically, the problem seems to be that when hard regs are *already*
assigned, prior to IRA (say because they are function parameters or
return values), then the allocator does not even consider the
possibility of moving that value to another register unless it
absolutely has to. It will merrily choose the worst possible option just
because it's the easiest decision.
Merged FSF GCC 4.5 into Linaro GCC 4.5. Likewise for 4.6. Pushed the
branches to Launchpad for testing. The 4.5 testing did not come back
totally clear, so this may delay the release a little. Hmmm.
Updated my FSF GCC 4.7 checkout and rebuilt it. This time the build
succeeded, so I've used it as the basis for a shiny new launchpad branch
"lp:gcc-linaro/4.7". I've created the release series to go with it.
Applied my new 64-bit shifts patch to the new GCC 4.7 Linaro branch and
submitted a merge request. This is mostly for the purposes of getting
the test results at this point.
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