On Jul 25, 2014, at 11:22 PM, "Panshilin (Peter)" <peter.panshi...@hisilicon.com<mailto:peter.panshi...@hisilicon.com>> wrote:
Hi all concerned: this test code I given below: AARCH32 [https://email-cn04.huawei.com/owa/14.3.158.1/themes/base/pgrs-sm.gif] Test function[cid:(null)][cid:(null)] { volatile unsigned int val0 = 0; volatile unsigned int val1 = 0; asm volatile("mrrc p15, 1, %0, %1, c15" : "=r"(val0), "=r"(val1)) val0 &= ~(1<<6); val1 &= ~(1<<6); asm volatile("mcrr p15, 1, %0, %1, c15" : "=r"(val0), "=r"(val1)); I think you want input to the above asm rather output. So asm volatile("mcrr p15, 1, %0, %1, c15" :: "r"(val0), "r"(val1)); Thanks, Andrew } After compiling, the result is: mrrc 15, 1, r2, r3, cr15 str r2, [fp, #-28] str r3, [fp, #-24] ldr r3, [fp, #-28] bic r3, r3, #64; str r3, [fp, #-28] ldr r3, [fp, #-24] bic r3, r3, #64 str r3, [fp, #-24] mcrr 15, 1, r2, r3, cr15 obviously , it is not what I expect. I have val0 an vl1 two vars, but the compiling result is only one val takes effect. especia I have to mention is AARCH32. thanks. Peter _______________________________________________ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org<mailto:linaro-toolchain@lists.linaro.org> http://lists.linaro.org/mailman/listinfo/linaro-toolchain
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