Also create field definitions for id_aa64pfr1 from ARMv8.5.
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
target/arm/cpu.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index a4d0174c05..02db6c5f5a 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1628,6 +1628,9 @@ FIELD(ID_AA64PFR0, GIC, 24, 4)
FIELD(ID_AA64PFR0, RAS, 28, 4)
FIELD(ID_AA64PFR0, SVE, 32, 4)
+FIELD(ID_AA64PFR1, BT, 0, 4)
+FIELD(ID_AA64PFR1, SBSS, 4, 4)
+
FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)
FIELD(ID_AA64MMFR0, BIGEND, 8, 4)
@@ -3267,6 +3270,11 @@ static inline bool isar_feature_aa64_lor(const
ARMISARegisters *id)
return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0;
}
+static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
+}
+
/*
* Forward to the above feature tests given an ARMCPU pointer.
*/
--
2.17.2
_______________________________________________
linaro-toolchain mailing list
linaro-toolchain@lists.linaro.org
https://lists.linaro.org/mailman/listinfo/linaro-toolchain
