Progress:
* UM-2 [QEMU upstream maintainership]
- respin and resend for a few patchsets after code review
* QEMU-422 [QEMU Arm Neoverse V1 vCPU for TCG]
- identified what the old ARMv8.5-CMODX feature is now
("prefetch speculation protection") and confirmed that
QEMU is already compliant with the instruction fetch ordering
requirements so there's no coding work required here
- Checked that we implement FEAT_ETS already and sent patches
to advertise it in the ID registers
- Checked that we already conform to the ordering rules required
by "prefetch speculation protection"
- Discovered that we accidentally fail to RAZ for a big chunk
of the reserved-for-new-AArch32-ID-registers space for v8 CPUs;
sent patches fixing that
thanks
-- PMM
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